[U-Boot-Users] [PATCH] 2/5: csb226 update

[Robert Schwebel]

csb226:

- bring in sync with innokom/memsetup.S
- fix MDREFR handling

Robert
-- 
 Dipl.-Ing. Robert Schwebel | http://www.pengutronix.de
 Pengutronix - Linux Solutions for Science and Industry
   Braunschweiger Str. 79,  31134 Hildesheim, Germany
   Handelsregister:  Amtsgericht Hildesheim, HRA 2686
    Phone: +49-5121-28619-0 |  Fax: +49-5121-28619-4
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diff -x CVS -x ptx-patches -urN u-boot/board/csb226/memsetup.S u-boot-ptx/board/csb226/memsetup.S
--- u-boot/board/csb226/memsetup.S	2003-03-06 16:53:05.000000000 +0100
+++ u-boot-ptx/board/csb226/memsetup.S	2003-03-31 10:51:00.000000000 +0200
@@ -38,6 +38,9 @@
    sub  pc,pc,#4
    .endm
 
+_TEXT_BASE:
+	.word	TEXT_BASE
+
 
 /*
  * 	Memory setup
@@ -222,23 +225,28 @@
         /* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
         /* ---------------------------------------------------------------- */
 
+        /* test if we run from flash or RAM - RAM/BDI: don't setup RAM      */
+	adr	r3, mem_init		/* r0 <- current position of code   */
+	ldr	r2, =mem_init
+	cmp	r3, r2			/* skip init if in place            */
+	beq	initirqs
+
 
 	/* ---------------------------------------------------------------- */
         /* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
         /* ---------------------------------------------------------------- */
 
 	/* Before accessing MDREFR we need a valid DRI field, so we set     */
-	/* this to power on defaults + DIR field.                           */
+	/* this to power on defaults + DRI field.                           */
 
-	ldr	r4,	=0x03ca4fff
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
-        ldr     r4,	[r1, #MDREFR_OFFSET]
+	ldr 	r3, 	=CFG_MDREFR_VAL
+	ldr	r2,	=0xFFF
+	and	r3,	r3, r2
+	ldr	r4,	=0x03ca4000
+	orr	r4,	r4,  r3
 
-	ldr	r4,	=0x03ca4030
 	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
-	ldr	r4,	[r1, #MDREFR_OFFSET]
-
-        /* Note: preserve the mdrefr value in r4                            */
+        ldr     r4,	[r1, #MDREFR_OFFSET]
 
 
 	/* ---------------------------------------------------------------- */
@@ -258,18 +266,16 @@
         /* Step 4: Initialize SDRAM                                         */
         /* ---------------------------------------------------------------- */
 
-	/* Step 4a: assert MDREFR:K1RUN and MDREFR:K2RUN and configure      */
+	/* Step 4a: assert MDREFR:K?RUN and configure                       */
 	/*          MDREFR:K1DB2 and MDREFR:K2DB2 as desired.               */
 
-	orr	r4,	r4,	#(MDREFR_K1RUN|MDREFR_K0RUN)
-
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,     [r1, #MDREFR_OFFSET]
-
+	ldr	r4,	=CFG_MDREFR_VAL
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
+	ldr	r4,	[r1, #MDREFR_OFFSET]
 
 	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
 
-	bic	r4,	r4,	#(MDREFR_SLFRSH)
+	bic	r4,	r4, #(MDREFR_SLFRSH)
 
         str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
         ldr     r4,     [r1, #MDREFR_OFFSET]