[U-Boot-Users] Memory problems with u-boot in EP852T board (Embedded Planet)

[Moshe Menachem]

> Hi All,
> 
> I'm porting u-boot to support the EP852T board of Embedded Planet(BUS @ 50MHz) .
> I saw that there is no reference for using this specific kind of board , but only u-boot for RPXLite board .
> 
> I encountered a problem to configure the u-boot correctly to support memory operation for this board .
> The EP 852T board uses a 8MB flash on CS0 (two chips of AMD - AM29LV320B, each is 4MB) and Micron SDRAM(MT48LC4M32B2) of 16MB on CS1 .
> 
> 1. Does CFG_MAX_FLASH_SECT  71(the num of sectors in one AMD chip) includes both chips ?
>     Which means does the u-boot/cpu see a 1 big flash of 8MB 32 bits bus with doubled size sector? instead of a 64KB size sectors(in a single AMD chip), a 128KB size   
>     sectors?
> 
> 2. According to the EP852T board user manual, the 8MB flash base address starts at 0xff800000 (=CFG_FLASH_BASE) .
>     I configured: 
>    CFG_FLASH_BASE	0xff800000
>    CFG_MONITOR_BASE  CFG_FLASH_BASE
>    CFG_BR0_PRELIM     0xff800001   (in order to support base address 0xff800000 for 8MB Flash size)
>    CFG_OR0_PRELIM	0xff800140   (OR Address mask of 0xff8000 for 8MB flash @50MHz)
> 
> 3. The SDRAM configuration :
>     SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
>     SDRAM_MAX_SIZE		0x01000000	/* max 16 MB */
>     CFG_PRELIM_OR_AM         0xfc000000
>     CFG_OR_TIMING_SDRAM	0x00000E00
>     CFG_OR1_PRELIM   ( CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
>     CFG_BR1_PRELIM   ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )   		 (=0x00000081)
>     
> 
> The problems i encountered :
> 
> 1. Although the flash prelim and mask are conifgured as defined in the EP board manual, when running the u-boot flash_get_size() 
>    it fails on reading Manufacturer ID.
>    When i bypass the flash_get_size and choose manually, in the code, the AM29LV320B flash and its sectors(71) and size(8MB),
>   later, in the u-boot monitor i cannot erase the flash (none of the u-boot erase options work), but i can only read its sectors content .
>   i also see that most of its sectors are detected as protected :(using the "flinfo" command)
> 
>  Bank # 1: AMD AM29LV320B (32 Mbit, bottom boot sect)
>   Size: 8 MB in 71 Sectors
>   Sector Start Addresses:
>     FF800000      FF804000      FF808000      FF80C000      FF810000     
>     FF814000      FF818000      FF81C000      FF820000      FF840000 (RO)
>     FF860000 (RO) FF880000 (RO) FF8A0000 (RO) FF8C0000 (RO) FF8E0000 (RO)
>     FF900000 (RO) FF920000 (RO) FF940000 (RO) FF960000 (RO) FF980000 (RO)
>     FF9A0000 (RO) FF9C0000 (RO) FF9E0000 (RO) FFA00000 (RO) FFA20000 (RO)
>     FFA40000 (RO) FFA60000 (RO) FFA80000 (RO) FFAA0000 (RO) FFAC0000 (RO)
>     FFAE0000 (RO) FFB00000 (RO) FFB20000 (RO) FFB40000 (RO) FFB60000 (RO)
>     FFB80000 (RO) FFBA0000 (RO) FFBC0000 (RO) FFBE0000 (RO) FFC00000 (RO)
>     FFC20000 (RO) FFC40000 (RO) FFC60000 (RO) FFC80000 (RO) FFCA0000 (RO)
>     FFCC0000 (RO) FFCE0000 (RO) FFD00000 (RO) FFD20000 (RO) FFD40000 (RO)
>     FFD60000 (RO) FFD80000 (RO) FFDA0000 (RO) FFDC0000 (RO) FFDE0000 (RO)
>     FFE00000 (RO) FFE20000 (RO) FFE40000 (RO) FFE60000 (RO) FFE80000 (RO)
>     FFEA0000 (RO) FFEC0000 (RO) FFEE0000 (RO) 01010101 (RO) 01010101 (RO)
>     01F40000 (RO) FFF60000 (RO) FFF80000 (RO) FFFA0000 (RO) FFFC0000 (RO)
>     FFFE0000 (RO)
> 
> 2. The second problem i have is with the SDRAM operation .
>     The SDRAM seems to work(read and write are possible) only when i use CFG_PRELIM_OR_AM   0xfc000000,
>     although CFG_PRELIM_OR_AM should be configured to 0xff000000 , for 16MB SDRAM OR mask .
> 
> Thanks in advance, 
> Moshiko
>      
> 
>       
> 
> 
> 
> 
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