[U-Boot-Users] Re: One more step to conclude the u-boot port to pxa255 board

[Wolfgang Denk]

In message <41C0A901.6080308 at topcomm.com.br> you wrote:
> 
> Now that everything is working with BDI plugged and u-boot transferred 
> to Flash Memory 0x00000000 address. With BDI we issue "reset" and 
> "go"and u-boot comes up and boots the kernel(one more "go") and linux 
> root file system from flash.
> 
> When we unplugged the BDI2000 and powered-up the board u-boot did not 
> come up.

This means that your BDI config file contains certain  initialization
sequences which are missing in U-Boot.

> seems that the u-boot is not prepared to be booted (0x00000000 entry 
> point) at power-up.

No. It is.

> Are we missing anything ? Any suggestions to solve this problem ?

See below.

> #define CONFIG_PXA250        1    /* This is an PXA250 CPU    */
> #define CONFIG_LUBBOCK        1    /* on an LUBBOCK Board        */

You said that this is  a  PXA255  on  a  custom  board.  Why  do  you
configure for a PXA250 on a Lubbock board then?

> #define CONFIG_COMMANDS        
> (CFG_CMD_BDI|CFG_CMD_LCDDRAW|CFG_CMD_LCDTST|CFG_CMD_LOADS|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_CACHE|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_BOOTD|CFG_CMD_CONSOLE|CFG_CMD_ASKENV|CFG_CMD_RUN|CFG_CMD_ECHO|CFG_CMD_REGINFO|CFG_CMD_IMMAP|CF
> G_CMD_DHCP|CFG_CMD_AUTOSCRIPT|CFG_CMD_ELF|CFG_CMD_MISC|CFG_CMD_SDRAM|CFG_CMD_DIAG|CFG_CMD_SAVES|CFG_CMD_PING|CFG_CMD_FAT|CFG_CMD_IMLS)

Do you really think anybody can read this code?

> #define CONFIG_ETHADDR        00:d0:c9:60:87:aa

It is an extremely bad idea to hard-wire the MAC address in U-Boot.

> #define CFG_DRAM_BASE        0xa0000000
> #define CFG_DRAM_SIZE        0x02000000
> 
> #define CONFIG_NR_DRAM_BANKS    4       /* we have 1 bank of DRAM */


Please read this line. There is at least  one  serious  bug  in  this
line.

> #define PHYS_SDRAM_1        0xa0000000 /* SDRAM Bank #1 */
> #define PHYS_SDRAM_1_SIZE    0x02000000 /* 32 MB */
> #define PHYS_SDRAM_2        0xa4000000 /* SDRAM Bank #2 */
> #define PHYS_SDRAM_2_SIZE    0x00000000 /* 0 MB */
> #define PHYS_SDRAM_3        0xa8000000      /* SDRAM Bank #3             */
> #define PHYS_SDRAM_3_SIZE    0x00000000      /* 0 MB                 */
> #define PHYS_SDRAM_4        0xac000000      /* SDRAM Bank #4             */
> #define PHYS_SDRAM_4_SIZE    0x00000000      /* 0 MB                 */

Adding  these  numbers  makes   me   believe   your   definition   of
CFG_DRAM_SIZE might be completely bogus.

Best regards,

Wolfgang Denk

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