[U-Boot-Users] Removing duplicate "FPGA Support" notes from the README file

[Jon Diekema]

Product:

- u-boot

Version:

- 1.0.2

CHANGELOG:

* Patch by Jon Diekema, 14 Jeb 2004:
  - Removing duplicate "FPGA Support" notes from the README file.
    This section is repeated twice in the README file.

CVS Comments:

- Removing duplicate "FPGA Support" notes

-- 
-------------------\\----------------------\\----------------------------
Jon Diekema         |  Custom IDEAS         |  http://www.cideas.com/
diekema at cideas.com  |  Grand Rapids, MI     |
-------------- next part --------------
To: wd at denx.de,u-boot-users at lists.sourceforge.net

Product:

- u-boot

Version:

- 1.0.2

CHANGELOG:

* Patch by Jon Diekema, 14 Jeb 2004:
  - Removing duplicate "FPGA Support" notes from the README file.
    This section is repeated twice in the README file.

CVS Comments:

- Removing duplicate "FPGA Support" notes

Patched files:

--- README	8 Feb 2004 22:55:39 -0000	1.72
+++ README	14 Feb 2004 14:49:45 -0000
@@ -1157,60 +1157,6 @@ The following options need to be configu
 
 		CONFIG_FPGA
 
-		Used to specify the types of FPGA devices. For
-		example,
-		#define CONFIG_FPGA  CFG_XILINX_VIRTEX2
-
-		CFG_FPGA_PROG_FEEDBACK
-
-		Enable printing of hash marks during FPGA
-		configuration.
-
-		CFG_FPGA_CHECK_BUSY
-
-		Enable checks on FPGA configuration interface busy
-		status by the configuration function. This option
-		will require a board or device specific function to
-		be written.
-
-		CONFIG_FPGA_DELAY
-
-		If defined, a function that provides delays in the
-		FPGA configuration driver.
-
-		CFG_FPGA_CHECK_CTRLC
-
-		Allow Control-C to interrupt FPGA configuration
-
-		CFG_FPGA_CHECK_ERROR
-
-		Check for configuration errors during FPGA bitfile
-		loading. For example, abort during Virtex II
-		configuration if the INIT_B line goes low (which
-		indicated a CRC error).
-
-		CFG_FPGA_WAIT_INIT
-
-		Maximum time to wait for the INIT_B line to deassert
-		after PROB_B has been deasserted during a Virtex II
-		FPGA configuration sequence. The default time is 500 mS.
-
-		CFG_FPGA_WAIT_BUSY
-
-		Maximum time to wait for BUSY to deassert during
-		Virtex II FPGA configuration. The default is 5 mS.
-
-		CFG_FPGA_WAIT_CONFIG
-
-		Time to wait after FPGA configuration. The default is
-		200 mS.
-
-- FPGA Support: CONFIG_FPGA_COUNT
-
-		Specify the number of FPGA devices to support.
-
-		CONFIG_FPGA
-
 		Used to specify the types of FPGA devices.  For example,
 		#define CONFIG_FPGA  CFG_XILINX_VIRTEX2