[U-Boot-Users] [PATCH] MPC85XXADS-20040716.patch for TLB/DDR
jdl at freescale.com
Fri Jul 16 21:06:01 CEST 2004
Here is a patch for the MPC8540/8560ADS and STXGP3 boards
that is primarily to support larger DDR memories up to 2G.
This patch applies with a -p2, and was tested on MPC8540ADS,
MPC8560ADS, and compiles on STXGP3 and SBC8560.
As usual, please let me know of any corrections needed here.
* Patch by Jon Loeliger, 16-Jul-2004:
Fixes for the MPC8540ADS, MPC8560ADS, and stxgp3 boards:
* Includes Dan Malek's mods of my mods for large DDR on STXGP3
* Updated OR3 to only use 1M, not 16M, for CADMUS. Thanks York!
* Made MPC8540/8560ADS be 33Mhz PCI by default.
* Incorporated Tom Armistead's spd_sdram patches for picosecond
resolution, banksize calculations, and dynamic DDR sizing.
* Better TLB and LAWBAR size determination.
* Reworked the TLB setup to support up to 2G DDR.
* DDR setup without SPD_EEPROM is not fully supported.
* Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
and CONFIG_L2_INIT_RAM options.
* Refactor Local Bus initialization out of SDRAM setup.
* Re-implement new version of LBC11/DDR11 errata workarounds.
* Moved board specific PCI init parts out of CPU directory.
* Added TLB entry for PCI-1 IO Memory
* Updated README.mpc85xxads
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