[U-Boot-Users] PQ2FADS-VR 2nd Ethernet

[Yuli Barcohen]

>>>>> Jihua Cheng writes:

    Jihua> Yuli, Thanks very much!

    Jihua> Here is the sympotoms.

    Jihua> Based on the PQ2FADS-VR schematic, I route parallel portC pin
    Jihua> PC17(Clk 15 for RX) and pin PC16(Clk16 for TX) for
    Jihua> FCC3. PortB PB4~PB17 are enabled for FCC3. When I use ping
    Jihua> command, I got "fec: tx error!" message in the console. I
    Jihua> found the message is from fec_send(...) at
    Jihua> cpu/mpc8260/ether_fcc.c. It seems CPM did not send out the
    Jihua> data to Phy.

This usually indicates that there is no Tx clock, probably because the
PHY does not provide it.

    Jihua> 1) I check BCSR3. Both FETHIEN2 and FETH2_RST are 1.

FETHIEN2=1 means that the PHY is isolated after power-up. This is not
what you want. Set FETHIEN2 to zero and reset PHY by toggling FETH2_RST.

    Jihua> 2) Phy Register seems OK (Reg0 = 0x2100, reg1 = 0x7809).

It's not completely OK because auto-negotiation is disabled. It's can be
a result of above mentioned isolation. Check what happens after enabling
the PHY, and set as necessary.

    Jihua> 3) I check PortB PB4~PB17. Dedicated Pin setting seems OK.

    Jihua> Where do I need to check?

    Jihua> I appreciate your help!


-- 
========================================================================
 Yuli Barcohen       | Phone +972-9-765-1788 |  Software Project Leader
 yuli at arabellasw.com | Fax   +972-9-765-7494 | Arabella Software, Israel
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