[U-Boot-Users] Gigabit Ethernet?

[Travis Sawyer]

John et al:

See inline below...
On Thu, 2004-03-11 at 23:59, John Clemens wrote:
> and having to write specific
> code for each phy, whose documentation may or may not be publically
> available is.. well, scary...

I concur full heartedly!!!
> 
> Phy register 0x0A looks promising.. does anyone know of a gigabit phy that
> doesn't support that register for 1000bT mode? specifically bits 10/11.
> (see a Cicada datasheet here:
> http://www.cicada-semi.com/products/lan/CIS8201/CIS8201_Data_Sheet_Rev_1_2_2.pdf)
> I don't know about marvell (no docs).
> 
The cicada spec says:  (paraphrasing here):  Shaded registers (0x00 -
0x0f) indicate standard MII registers.  All unshaded registers are
optional registers, per the IEEE 802.3 standard.


> Seems like we should be able to use those bits like the bits in register
> 0x5 for 10/100 modes... and my gut tells me that register is in a spec
> somwhere..

The LXT9262/9782 spec says:  Base registers (0 through 8) are in
accordance with... Additional rgisters (16 through 22) are defined in
accordance with IEEE 802.3 specification for adding _*unique chip
functions*_

Specifically, registers 9 and 10 (1000Base-T/100Base-T2 Control and
status) are not implemented.

The lxt spec does not indicate what reads to these registers would
result in, but for giggles I tried it out.

Using my ocotea board (4 ethernet ports, 0 & 1 are 10/100 and 2 & 3 are
10/100/1000).   Phy for port 0 is at address 0x01, and phy for port 2 is
at 0x10.  Since the board has 4 phy chips, the mii info is a bit
cluttered. (Note the lxt is a 6 port phy)

Please note, I currently don't have any hacks in for GbE support so mii
info incorrectly states that phy 0x10 is at 100Mb/s.

=> mii info
PHY 0x00: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX
PHY 0x01: OUI = 0x04DE, Model = 0x08, Rev = 0x07, 100baseT, FDX
PHY 0x02: OUI = 0x04DE, Model = 0x08, Rev = 0x07,  10baseT, HDX
PHY 0x03: OUI = 0x04DE, Model = 0x08, Rev = 0x07,  10baseT, HDX
PHY 0x04: OUI = 0x04DE, Model = 0x08, Rev = 0x07,  10baseT, HDX
PHY 0x05: OUI = 0x04DE, Model = 0x08, Rev = 0x07,  10baseT, HDX
PHY 0x06: OUI = 0x04DE, Model = 0x08, Rev = 0x07,  10baseT, HDX
PHY 0x10: OUI = 0x03F1, Model = 0x01, Rev = 0x03, 100baseT, FDX
PHY 0x18: OUI = 0x03F1, Model = 0x01, Rev = 0x03,  10baseT, HDX
=> mii read 1 0
3100
=> mii read 1 1
7829
=> mii read 1 9
FFFF
=> mii read 1 a
FFFF
=> mii read 10 0
1140
=> mii read 10 1
796D
=> mii read 10 9
0300
=> mii read 10 a
7C00
=>


So, the LXT reports FFFF for the unimplented registers, the cicada
properly reports Link partner capable of 1000FDX & 1000HDX in register
0xA


So, if the IEEE802.3 spec. say unimplemented registers return F's we're
in business.  Anyone have the spec handy???

> > > > Is anyone working on Gigabit Ethernet PHY support for u-boot?
> > >
-travis