[U-Boot-Users] v2p4 porting troubles

[Joakim Tjernlund]

> In message <009b01c40baa$a324f2b0$cb01a8c0 at xiphos.ca> you wrote:
> > We're doing quite the tag team here.
>
> ;-)
>
> > The code from Xilinx is as follows...
> >
> > void XIo_Out32(XIo_Address OutAddress, Xuint32 Value)
> > {
> >    __asm__ volatile ("stw %0,0(%1); eieio" : : "r" (Value), "r"
> > (OutAddress));
> > }
>
> This code is broken. The "r" operand specification sais  "a  register
> operand  is  allowed  provided  that it is in a general register." Of
> course R0 is a GPR as well. I think you need to use "m" (any kind  of
> address that the machine supports in general) here:
>
>      __asm__ volatile ("stw %0,0(%1); eieio" : : "r" (Value), "m" (OutAddress));
>

If you want to avoid using R0, you should be able to use the "clobber" list.
like this:
__asm__ volatile ("stw %0,0(%1); eieio" : : "r" (Value), "r" (OutAddress) : "r0" );

 Jocke