[U-Boot-Users] Help Debugging U-Boot _start in Start.S

[Bradley Remedios]

Hello all,

I'm trying to debug some changes that I've done to U-Boot.

My first problem is that for some reason I keep getting what I believe
to be a Machine Check Exception as the code is jumping to 0x200 (set
in ivor1).  In _start during the setup of the Stack in ISRAM, there
are two instructions, the second of which according to the comment
terminates the call chain.  I have included the code snippet below.

 	lis	r1,CFG_INIT_RAM_ADDR at h
	ori	r1,r1,CFG_INIT_SP_OFFSET at l

	li	r0,0
	stwu	r0,-4(r1)
	stwu	r0,-4(r1)		/* Terminate call chain */

The first stwu r0,-4(r1) succeeds but the second one causes a Machine
Check Exception to occur.  r0 = 0, and r1 = 0xC0001F80 prior to the
instruction being ran.  Shouldn't CFG_INIT_RAM_ADDR be 0x80000000 as
0xC0000000 will get mapped to 0x80000000 will it not?  I have tried
this code with CFG_INIT_RAM_ADDR as 0xC0000000 (original) and
0x80000000 but both have the same result.

The documentation for the 440GP states that this is caused by either a
timeout or error on the reading or writing of data or instructions on
the PLB Interface.  I haven't changed any of the timing information
for the Peripherals as I was given an configuration for the Ebony
board from USI (Abatron Dealer) so that should be fine.

My other problem is that occasionally (using same binaries and
debugging steps) I get a program check  as soon as MSR[ME] and MSR[CE]
are enabled at the beginning of _start.

My last question is, that unless maybe I'm misunderstanding how the
TLB is setup, no interrupt vectors for exceptions will be loaded at
the addresses at which the Machine Check Exception is occuring at.  I
have included my understanding of the mapping of addresses below.

Why is MSR[ME] enabled if there is no vector setup to handle it?

I have done the following changes to the Ebony platform:
1. Addresses have been changed.  Entry point = 0x3000 TEXT_BASE = 0x00004000
2. TLB setup has been removed (our platform should do entire TLB
Setup.) and moved into the Abatron configuration file (section below)
3. board/ebony/ebony.c no longers sets up SDRAM.

My Setup:
Debugger: Abatron BDI2000
Toolchain: ELDK
TLB Configuration in Abatron Unit:
     WTLB    0xF0000095  0x1F00003F  ;Boot Space 256MB
     WTLB    0x00000098  0x0000003F  ;SDRAM 256MB @ 0x00000000
     WTLB    0xE0000095  0x1F00001B  ;Peripheral, 256MB
     WTLB    0xC0000010  0x0800003F  ; ISRAM1
     WTLB    0xC0001010  0x0800103F  ; ISRAM2
     WTLB    0xD0000095  0x2000001B  ; PCI Base
     WTLB    0x80000095  0x3000001B  ; PCI Mem Base

My understanding of Memory Mapping by TLB:
Physical -> Virtual
0xF0000000 -> 0xF0000000 ERPN=1
0xE0000000 -> 0x40000000 ERPN=1 // Peripheral Base
0xC0000000 -> 0x80000000 ERPN=0 // ISRAM
0x00000000 -> 0x00000000 ERPN=0 // SDRAM
0xD0000000 -> 0x00000000 ERPN=2 // PCI Base
0x80000000 -> 0x00000000 ERPN=3 // PCI Membase

All of my changes are configurable.  My main purpose of this
modification is to enable U-Boot to be copied and ran from SDRAM
directly.
-- 
Bradley Remedios
bremedios at gmail.com