[U-Boot-Users] RPXlite_DW problem/solution U-boot CVS

[Wolfgang Denk]

In message <200411292219.25317.ccool at ninjatech.biz> you wrote:
> 
> I found out a little something in the CVS version of U-boot about the 
> RPXlite_DW addapted by Sam Song.
> 
> In the file 
> include/configs/RPXlite_DW.h
> at line 324
> I had to replace
> #define CFG_OR1_PRELIM	( CFG_OR_AM_SDRAM | CFG_OR_TIMING_SDRAM )
> for
> #define CFG_OR1_PRELIM          0xFF000E00
> 
> and at line 353-354
> I had to replace
> #define CFG_MAMR_9COL  ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
> 			MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10)
> by
>  #define CFG_MAMR_9COL 0x20802000

Argh... Is it too much to ask you to provide the information  in  the
same  readable  format  as  used  in the original coinfig file, i. e.
broken down into separate, readable parts, instead of just throwing a
hard-coded hex number on us?

> If I did not change those two register, U-boot would get stuck at the DRAM
> detection and would only find 1K (instead of the 16M on my board).

So let's have a look what you did.

You changed the OR setting from  0xF800....  into  0xFF00....,  which
means  that instead oif the previously used mapping of 128 MB you now
only map 64 MB. [I really wonder why you not redefined SDRAM_MAX_SIZE
as 0x04000000 - was too much work or what?]

And you changed MAMR_AMA_TYPE_1 into MAMR_AMA_TYPE_0  (Addess  Multi-
plexing Type 0), and MAMR_G0CLA_A10 into MAMR_G0CLA_A11 (General Line
0 : A10).

And you still use the name CFG_MAMR_9COL for this  definition,  which
is  misleading at best, because what you changed means that you don't
have a 9 column SDRAM on your board, but are using a 8 column SDRAM.

> I`m sending this as a simple information.  I know my method is not the best
> way to define thoses register, but I though that maybe the other ways to 

Indeed, it is not the best way. Actually it is a quick and ugly  hack
and  not  usable,  as  it breaks U-Boot for all the other boards that
worked fine so far.



What we learned is that there seems to be RPXlite_DW boards out there
that use 8 column SDRAM, and others (most?) that use 9 column  SDRAM.
The  correct  fix  to  this would be to make the SDRAM initialization
code automatically detect if 8 or 9 column SDRAM is used  and  adjust
the  settings  as  needed. Example code for doing exactly this can be
found in the TQM8xxL configurations (i. e. in board/tqm8xx/tqm8xx.c).

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Monday is an awful way to spend one seventh of your life.