[U-Boot-Users] u-boot debug failure with BDI2000 on MPC8540ads and eval8540 (gdatech's 8540 board)
emre kara
emrekara2002 at yahoo.co.uk
Fri Dec 9 13:33:19 CET 2005
Dear All;
I have bought a BDI2000 with BDIGDB-85xx s/w. I'll use
it for
freescale's mpc8540eval board (know as GDA8540) and
freescale's
MPC8560ads. I can succesfully program the flash, but I
can't debug neither linux kernel (2.6.15) nor
u-boot(version 1.1.3).
We have already running systems included u-boot and
linux,so I
could (try) to debug both of them.
There is a strange behavior while debugging u-boot.
Target boots at (loop) state, a few steps later (with
ti command or step
on gdb),bdi2000 gives a error message "Core status is
0x0041 *** Core is
stopped, no restart possible bdi2000" loses control
over target and then
it reads all the register zero, every
time on the same address(0xfffff154) it happes
again,any breakpoint
greater then this address doesnt work. I have tried it
3 different
versions of u-boot (1.1.2-1.1.3-and latest with CVS)
programmed on flash,
and 2 different hardwares, nothing has changed.
Normally, all this u-boot images succcesfully can boot
up the target(with
reset run command) and all of them are fully
functional.
Can you please examine the log below?
------------------------------------------------
- TARGET: waiting for target Vcc
- TARGET: processing power-up delay
- TARGET: processing user reset request
- BDI asserts HRESET
- Reset JTAG controller passed
- JTAG exists check passed
- IDCODE is 0x1007001D
- SVR is 0x80700020
- PVR is 0x80200020
- Core status is 0x0001
- Platform status is 0x0005
- SAP status is 0x0005
- CCSRBAR is 0x0_ff700000
- BDI scans platform HALT command
- Core status is 0x0001
- Platform status is 0x0005
- SAP status is 0x0005
- BDI removes HRESET
- BDI writes boot loop to L2SRAM
- BDI scans platform RESUME command
- TARGET: Target PVR is 0x80200020
- TARGET: resetting target passed
- TARGET: processing target startup ....
- TARGET: processing target startup passed
BDI>conf
BDI MAC : 00-0c-01-97-95-07
BDI IP : 192.168.11.101
BDI Subnet : 255.255.255.255
BDI Gateway : 255.255.255.255
Config IP : 192.168.11.1
Config File : ads8560.cfg
BDI>i
Target CPU : MPC8560/8540 Rev.2
Target state : halted
Debug entry cause : COP halt
Current PC : 0xfffffffc
Current CR : 0x00000000
Current MSR : 0x00000200
Current LR : 0x00000000
Current CCSRBAR : 0x0_40000000
BDI>bi 0xfffff14c
Breakpoint identification is 0
BDI>go
- TARGET: stopped
BDI>i
Target CPU : MPC8560/8540 Rev.2
Target state : halted
Debug entry cause : instruction breakpoint
Current PC : 0xfffff14c
Current CR : 0x40000000
Current MSR : 0x00000200
Current LR : 0x00000000
Current CCSRBAR : 0x0_40000000
BDI>ti
Target CPU : MPC8560/8540 Rev.2
Target state : halted
Debug entry cause : single step
Current PC : 0xfffff150
Current CR : 0x40000000
Current MSR : 0x00000200
Current LR : 0x00000000
Current CCSRBAR : 0x0_40000000
BDI>ti
Target CPU : MPC8560/8540 Rev.2
Target state : halted
Debug entry cause : single step
Current PC : 0xfffff154
Current CR : 0x40000000
Current MSR : 0x00000200
Current LR : 0x00000000
Current CCSRBAR : 0x0_40000000
BDI>ti
- Core status is 0x0041
*** Core is stopped, no restart possible
# PPC: timeout while waiting for halt
BDI> Target CPU : MPC8560/8540 Rev.2
Target state : halted
Debug entry cause : COP freeze
Current PC : 0x00000000
Current CR : 0x00000000
Current MSR : 0x00000000
Current LR : 0x00000000
Current CCSRBAR : 0x0_40000000
# Step timeout detected
BDI>i
Target CPU : MPC8560/8540 Rev.2
Target state : halted
Debug entry cause : COP freeze
Current PC : 0x00000000
Current CR : 0x00000000
Current MSR : 0x00000000
Current LR : 0x00000000
Current CCSRBAR : 0x0_40000000
BDI>
and system craches until a "reset run" command
---------------------------------------------------------------------
What can be cause this problem?.
The configuration file of eval8540 is below (taken
from ultsol web site).
Abatron Model:BDI2000/C
SerNo: 97950725
Loader: V1.05
Firmware:V1.04 bdiGDB for MPC85xx
Logic:V1.05 PPC6xx/PPC7xx
;bdiGDB configuration file for Metrowerks eval board
MPC8540
;-----------------------------------------------------------
;
; The boot flash data bus is connected with swapped
bytes.
;
; CPU D0 D1 ... D6 D7 | D8 D9 ... D14 D15
; | | ... | | | | ... | |
; | | ... | | | | ... | |
; FLASH D7 D6 ... D1 D0 | D15 D14 ... D9 D8
;
;
;
[INIT]
; init core register
;
; define maximal transfer size
;TSZ4 0x00000000 0xffffffff
;
; Move the L2SRAM to the initial MMU page
WM32 0xFF720000 0x68010000 ;L2CTL
WM32 0xFF720100 0xFFFC0000 ;L2SRBAR0
WM32 0xFF720000 0xA8010000 ;L2CTL
;
; Clear l2 sram with dma (needed if STARTUP HALT)
;WM32 0xff721110 0x00040000 ;SATR0
SREADTTYPE=Read, don't
snoop
;WM32 0xff721114 0xff700004 ;SAR0
Dummy source register
;WM32 0xff721118 0x00050000 ;DATR0
DWRITETTTYPE=Write, snoop
local processor
;WM32 0xff721120 0x00040000 ;BCR0
Size
;WM32 0xff721100 0x0f009404 ;MR0
BWC=f,SAHTS=2(4
bytes),SAHE=1,SWSM=Dest,SRW=1,CTM=1,CS=0
;WM32 0xff72111c 0xfffc0000 ;DAR0
which sets CS=1
;DELAY 200 ;let DMA
complete
;
; load and execute boot code (needed if STARTUP HALT)
;WM32 0xfffffffc 0x48000000 ;loop
;EXEC 0xfffffffc 1000
;
; load TLB entries, helper code @ 0xfffff000
WM32 0xfffff000 0x7c0007a4 ;tlbwe
WM32 0xfffff004 0x7c0004ac ;msync
WM32 0xfffff008 0x48000000 ;loop
;
; 1MB TLB1 #1 0x40000000 - 0x400fffff
WSPR 624 0x10010000 ;MAS0:
WSPR 625 0x80000500 ;MAS1:
WSPR 626 0x4000000a ;MAS2:
WSPR 627 0x40000015 ;MAS3:
WSPR 628 0x00000000 ;MAS4:
EXEC 0xfffff000
;
; 64 MB TLB1 #2 0xc0000000 - 0xc3ffffff
WSPR 624 0x10020000 ;MAS0:
WSPR 625 0x80000800 ;MAS1:
WSPR 626 0xc0000008 ;MAS2:
WSPR 627 0xc0000015 ;MAS3:
EXEC 0xfffff000
;
; 64 MB TLB1 #3 0x00000000 - 0x03ffffff
WSPR 624 0x10030000 ;MAS0:
WSPR 625 0x80000800 ;MAS1:
WSPR 626 0x00000008 ;MAS2:
WSPR 627 0x00000015 ;MAS3:
EXEC 0xfffff000
;
; 64 MB TLB1 #4 0x04000000 - 0x07ffffff
WSPR 624 0x10040000 ;MAS0:
WSPR 625 0x80000800 ;MAS1:
WSPR 626 0x04000008 ;MAS2:
WSPR 627 0x04000015 ;MAS3:
EXEC 0xfffff000
;
; 16 MB TLB1 #5 0xff000000 - 0xffffffff
WSPR 624 0x10050000 ;MAS0:
WSPR 625 0x80000700 ;MAS1:
WSPR 626 0xff80000a ;MAS2: changed
WSPR 627 0xff800015 ;MAS3: changed
EXEC 0xfffff000
;
; 16 MB TLB1 #0 0xf0000000 - 0xf0ffffff
WSPR 624 0x10000000 ;MAS0:
WSPR 625 0x80000700 ;MAS1:
WSPR 626 0xf0000008 ;MAS2:
WSPR 627 0xf0000015 ;MAS3:
EXEC 0xfffff000
;
; Remove the L2SRAM from the initial MMU page
WM32 0xFF720000 0x28010000 ;L2CTL
WM32 0xFF720000 0x28000000 ;L2CTL
;
; Move CCSRBAR to 0xfdf00000
WM32 0xff700000 0x000fdf00 ;CCSRBAR to
0xfdf00000
;
; Initialize LAWBAR's
WM32 0xfdf00C08 0x00000000 ;LAWBAR0 :
@0x00000000
WM32 0xfdf00C10 0x80f0001b ;LAWAR0 :
DDR/SDRAM 256MB
;WM32 0xfdf00C28 0x000c0000 ;LAWBAR1 :
@0xc0000000
;WM32 0xfdf00C30 0x8040001d ;LAWAR1 :
Local Bus 1GB
;
; Setup DDR (Metrowerks eval board, 256MB DDR)
WM32 0xfdf02000 0x00000007 ;CS0_BNDS
WM32 0xfdf02080 0x80000101 ;CS0_CONFIG
WM32 0xfdf02108 0x36342321 ;TIMING_CFG_1
WM32 0xfdf0210C 0x00000800 ;TIMING_CFG_2
WM32 0xfdf02110 0x02000000 ;DDR_SDRAM_CFG
WM32 0xfdf02118 0x00000062
;DDR_SDRAM_MODE
WM32 0xfdf02124 0x03d00100
;DDR_SDRAM_IVAL
DELAY 200
WM32 0xfdf02110 0xc2000000 ;DDR_SDRAM_CFG
;
; Setup Flash chip select
WM32 0xfdf05000 0xff801001 ;BR0
WM32 0xfdf05004 0xff806f67 ;OR0
;
; Setup flash programming workspace in L2SRAM
;WM32 0x40020000 0x68010000 ;L2CTL
;WM32 0x40020100 0xf0000000 ;L2SRBAR0
;WM32 0x40020000 0xA8010000 ;L2CTL
;WSPR 63 0xf0000000 ;IVPR to
workspace
;WSPR 415 0x0001500 ;IVOR15 :
Debug exception
;WM32 0xf0001500 0x48000000 ;write valid
instruction
;
; Setup for program execution
WM32 0xfdf20000 0x28010000 ;L2CTL
WM32 0xfdf20000 0x28000000 ;L2CTL
WSPR 63 0x00000000 ;IVPR to
workspace
WSPR 406 0x0000700 ;IVOR6 :
Program exception
WSPR 415 0x0001500 ;IVOR15 :
Debug exception
WM32 0x00000700 0x48000000 ;write valid
instruction
WM32 0x00001500 0x48000000 ;write valid
instruction
;
; Clear flash Lock-Bits
WM16 0xFF800000 0x6000 ;clear Lock-Bits
command
WM16 0xFF800000 0xD000
DELAY 1000 ;needs up to 0.7
sec
WM16 0xFF800000 0xFFFF ;set flash to read
mode
;
[TARGET]
;***DONE***
MMU XLAT
CPUTYPE 8540 ;the CPU type
JTAGCLOCK 3 ;use 4 MHz JTAG clock
STARTUP LOOP ;use boot loop in L2SRAM
;STARTUP HALT ;halt core while HRESET is
asserted
BREAKMODE SOFT ;SOFT or HARD, HARD uses
PPC hardware
breakpoint
STEPMODE JTAG ;JTAG or HWBP, HWBP uses a
hardware breakpoint
WAKEUP 200 ;give reset time to complete
;POWERUP 5000 ;start delay after power-up
detected in ms
POWERUP 100 ;start delay after power-up
detected in ms
MEMACCESS SAP ;use SAP or CORE for JTAG
memory accesses
[HOST]
IP 192.168.11.1
;emreFILE E:\cygwin\home\demo\e500\fibo.elf
;emreFORMAT ELF
;emreLOAD MANUAL ;load code MANUAL or AUTO
after reset
;emreDUMP
D:\SCORE_PRO\BRIDGE_CARD\BDI2000\DUMP\e500.bin
[FLASH]
CHIPTYPE STRATAX16
CHIPSIZE 0x800000 ;The size of one flash chip in
bytes
BUSWIDTH 16 SWAP ;The bytes are swapped !!!
WORKSPACE 0x00000000 ;workspace in system RAM
;WORKSPACE 0xf0000000 ;workspace in L2SRAM
;FILE E:\cygwin\home\bdidemo\e500\ads8560.cfg
;FORMAT BIN 0xFF800000
;ERASE 0xFF800000 ;erase sector 0
;ERASE 0xFF840000 ;erase sector 1
;ERASE 0xFF880000 ;erase sector 2
;ERASE 0xFF8C0000 ;erase sector 3
[REGS]
FILE $reg8560.def
Best Regards
Emre KARA
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