[U-Boot-Users] U-Boot CFI Flash driver incompleteness

Nikita V. Youshchenko yoush at cs.msu.su
Sun Dec 11 22:19:38 CET 2005


While porting U-Boot to a custom board, I faced a situation when U-Boot 
failed to write of erase to the board flash chip.

Flash chip is SG29GL32M10FAIR4 from Spansion, 
This is CFI-compatible NOR flash chip, that could be used both with 8-bit 
and 16-bit data bus, selected by hardware setup. In my case, it's in 8-bit 

With linux MTD subsystem, write and erase work as expected.
Here is what Linux drivers print about the chip when in verbose mode:

physmap flash device: 400000 at 18000000
Number of erase regions: 2
Primary Vendor Command Set: 0002 (AMD/Fujitsu Standard)
Primary Algorithm Table at 0040
Alternative Vendor Command Set: 0000 (None)
No Alternate Algorithm Table
Vcc Minimum:  2.7 V
Vcc Maximum:  3.6 V
No Vpp line
Typical byte/word write timeout: 128 ╣s
Maximum byte/word write timeout: 256 ╣s
Typical full buffer write timeout: 128 ╣s
Maximum full buffer write timeout: 4096 ╣s
Typical block erase timeout: 1024 ms
Maximum block erase timeout: 16384 ms
Chip erase not supported
Device size: 0x400000 bytes (4 MiB)
Flash Device Interface description: 0x0002
  - supports x8 and x16 via BYTE# with asynchronous interface
Max. bytes in buffer write: 0x20
Number of Erase Block Regions: 2
  Erase Region #0: BlockSize 0x2000 bytes, 8 blocks
  Erase Region #1: BlockSize 0x10000 bytes, 63 blocks
phys_mapped_flash: Found 1 x16 devices at 0x0 in 8-bit bank
 Amd/Fujitsu Extended Query Table at 0x0040
number of CFI chips: 1
cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness.

I examined u-boot CFI flash driver code, and the chip datasheet.
Looks like u-boot driver defines offsets at which commands are written to 
the flash as constants, while flash datasheet states the addresses are 
different in 8bit and 16bit modes.

I was able to make write and erase work by applying the following patch:

diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c
index 4b7a110..292bda7 100644
--- a/drivers/cfi_flash.c
+++ b/drivers/cfi_flash.c
@@ -107,9 +107,15 @@

 #define AMD_STATUS_TOGGLE              0x40
 #define AMD_STATUS_ERROR               0x20
 #define AMD_ADDR_ERASE_START           0x555
 #define AMD_ADDR_START                 0x555
 #define AMD_ADDR_ACK                   0x2AA
+#define AMD_ADDR_ERASE_START           0xAAA
+#define AMD_ADDR_START                 0xAAA
+#define AMD_ADDR_ACK                   0x555

 #define FLASH_OFFSET_CFI               0x55
 #define FLASH_OFFSET_CFI_RESP          0x10

and defining CONFIG_AMD_8BIT_FLASH in my board config file.

I don't know if this is specific to the chip used, or for all chips with 
AMD command set that work in 8bit mode. If later, maybe it's better to fix 
the driver to automatically use valid addresses depending on width of the 
data bus.

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