[U-Boot-Users] Zilog Z85230 serial communication controller

[Jerry Van Baren]

Häpe, Sebastian, HRD/AB wrote:
> Hi again!
> 
> Currently I try to integrate a Zilog Z85230 serial communication controller
> on a 603e-based board to work with U-Boot.

[snip]

> When I compile this, load it into RAM and execute it, everything is fine,
> MiniCom shows an 'I'.

I assume you are putting a stand-alone snippet of code in RAM -- in this 
case, your MMU and caches are disabled.

> Now I put this litte function into the file serial.c from U-Boot and compile
> it.
> Then I load U-Boot to Flash and run it. I'm tested before, wheather the
> function is always called and it is.
> 
> When I run it, I get an error, caused by the MMU, because it cannot
> translate the demanded address (it's a physical one).
> Now I tried to disable the data-address-translation on the beginning of the
> function and re-enable it at the end, always surrounded by an
> 'isync'-command. It this case, the program runs, but without any output via
> the serial port.
> 
> Is it legal to disable the MMU in this context and how should I configure
> U-Boot for my memory map? 
> 
> I have the following memory map on my board:
> 
> 0x00000000 - 0x007FEFFF SRAM
> 
> 0xF5000000 - Serial Interface #1 Channel B Control
> 0xF5000008 - Serial Interface #1 Channel B Data
> .
> .
> .
> 0xF50000D0 - Serial Interface #3 Channel A Control
> 0xF50000D8 - Serial Interface #3 Channel A Data
> 
> 0xFF800000 - 0xFFFFFFFF Flash
> 
> Thanks for ideas or advices why this doesn't work? 
> 
> Sebastian Häpe

It doesn't run from u-boot because you have not mapped the physical 
memory space using a BAT (or other MMU method).  You need to map the 
memory area _and mark it uncached_.

By disabling the MMU around the call, you got around the memory 
protection issue, but now you have a caching issue: u-boot will be 
running with data caching enabled (and instruction caching, but that 
shouldn't be a problem).  When you do your write to the control 
registers you are only writing to cache, not to the registers 
themselves.  There is no reason for the CPU to write your register-bound 
data to the registers, so you never see anything coming out.

The only way to make this work is to understand and use the MMU and 
cache control or disable them altogether (hint: disabling is not a good 
choice other than proof-of-concept testing :-).

* Do some User Manual reading on your processor, concentrating on the 
sections covering MMU (DBATs) and cache.

* Figure out which DBAT(s) are available for use and use one of them to 
map your peripheral space.

gvb