[U-Boot-Users] 7xx/74xx cache question
Jerry Van Baren
gerald.vanbaren at smiths-aerospace.com
Fri Jul 15 16:32:55 CEST 2005
Richard Danter wrote:
> Hi all,
> Further progress on my port. I can now write to flash!
> I noticed in lib_ppc/board.c board_init_r() that on e500 CPU's the
> unlock_ram_in_cache() function is called. The 7xx/74xx also locks the
> init RAM in the dcache, but nowhere is it unlocked.
> I tried calling unlock_ram_in_cache() from my board's misc_init_r()
> function, but this crashes U-Boot.
> As an experiment, I left the cache locked, but then ran the "dcache off"
> command from the shell. If I do printenv before turning the dcache off
> it is all OK, if I do it after then it crashes.
> With my debugger I can see that the gd data structure is garbage when
> env_get_char_memory() is called. But I thought all data was copied to
> the main sys RAM.
> Is there something else I need to do before/after calling
> unlock_ram_in_cache() so I can use the D-Cache as normal?
> PS Calling icache_enable() from misc_init_r() seems to work fine.
WRT data cache enabling, in order to enable data cache, you need to
first set up BATs and/or the MMU page tables. You need the MMU
configured and enabled so that you can mark I/O space(s) to be
uncached... by default every data access is cached which wreaks havoc
with I/O (to put it lightly :-).
I am not aware of anybody doing this in u-boot because it is a major
pain to do and minor benefit for the brief time you should be running in
u-boot (but likely someone has).
When you boot your OS (e.g. linux), the OS should do its own MMU set up
and data cache enabling.
WRT your locking question, I don't know.
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