[U-Boot-Users] [PATCH] fix [id]cache_status for MPC85xx processors

Murray.Jensen at csiro.au Murray.Jensen at csiro.au
Mon Jul 18 16:45:45 CEST 2005

The existing code for the [id]cache_status commands on MPC85xx processors
looks at the wrong bit to determine if the L1 cache is enabled. It looks
at the most significant bit when it should look at the least significant
bit. This patch corrects this bug. Cheers!


* Patch by Murray Jensen <Murray.Jensen at csiro.au>, July 19, 2005:
  - fix bug in [id]cache_status commands for MPC85xx processors; should
    look at LSB of L1CSRn registers to determine if L1 cache is enabled,
    not the MSB.


This patch is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free Software
Foundation; either version 2 of the License, or (at your option) any later
Murray Jensen, CSIRO Manufacturing & Infra. Tech.      Phone: +61 3 9662 7763
Locked Bag No. 9, Preston, Vic, 3072, Australia.         Fax: +61 3 9662 7853
Internet: Murray.Jensen at csiro.au

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