[U-Boot-Users] [PATCH]: MPC85XX-20050606-ddr-cpo.patch

[Jon Loeliger]

Wolfgang,

This patch fixes timing problems on for some speeds of
DDR I on 85XX boards.  It removes the setting of the CPO
field for the DDR I parts.

Thanks,
jdl



* Patch by Jon Loeliger, 06-Jun-2005
  On 85xx boards, don't set the CPO field of the DDR I controllers.



Index: cpu/mpc85xx/spd_sdram.c
===================================================================
RCS file: /cm/vault/u-boot/u-boot/cpu/mpc85xx/spd_sdram.c,v
retrieving revision 1.1.1.1.4.12
diff -u -r1.1.1.1.4.12 spd_sdram.c
--- cpu/mpc85xx/spd_sdram.c	5 May 2005 21:33:51 -0000	1.1.1.1.4.12
+++ cpu/mpc85xx/spd_sdram.c	6 Jun 2005 16:40:58 -0000
@@ -613,16 +613,19 @@
 	}
 
 	/*
-	 * Empirically set ~MCAS-to-preamble override.
+	 * Empirically set ~MCAS-to-preamble override for DDR 2.
 	 * Your milage will vary.
 	 */
-	if (effective_data_rate == 266 || effective_data_rate == 333) {
-		cpo = 0x7;		/* READ_LAT + 5/4 */
-	} else if (effective_data_rate == 400) {
-		cpo = 0x9;		/* READ_LAT + 7/4 */
-	} else {
-		/* Pure speculation */
-		cpo = 0xb;
+	cpo = 0;
+	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+		if (effective_data_rate == 266 || effective_data_rate == 333) {
+			cpo = 0x7;		/* READ_LAT + 5/4 */
+		} else if (effective_data_rate == 400) {
+			cpo = 0x9;		/* READ_LAT + 7/4 */
+		} else {
+			/* Pure speculation */
+			cpo = 0xb;
+		}
 	}
 
 	ddr->timing_cfg_2 = (0