[U-Boot-Users] u-boot support for MMC (ATR1RM9200) available or not?
D Cherkashin
divch at infoline.su
Sun Mar 6 02:22:44 CET 2005
----- Original Message -----
From: Wolfgang Denk <wd at denx.de>
To: D Cherkashin <divch at infoline.su>
Cc: <u-boot-users at lists.sourceforge.net>
Sent: Saturday, March 05, 2005 5:18 PM
Subject: Re: [U-Boot-Users] u-boot support for MMC (ATR1RM9200) available or
not?
> If in doubt, it always makes sense to check the CVS version.
CVS version u-boot, command
grep -r MMC *
output:
board/at91rm9200dk/at45.c: /* Set up PIO SDC_TYPE to switch on DataFlash
Card and not MMC/SDCard */
board/cmc_pu2/at45.c: /* Set up PIO SDC_TYPE to switch on DataFlash Card
and not MMC/SDCard */
board/omap1610inn/omap1610innovator.c: /* mux setup for SD/MMC driver */
board/omap1610inn/omap1610innovator.c: /* bit 13 for MMC2 XOR_CLK */
board/omap1610inn/omap1610innovator.c: /*2.75V for MMCSDIO1 */
board/omap1610inn/omap1610innovator.c: /* PullUps for SD/MMC driver */
board/omap2420h4/omap2420h4.c: muxSetupMMCSD();
board/omap2420h4/omap2420h4.c: * Routine: muxSetupMMCSD (ostboot)
board/omap2420h4/omap2420h4.c: * Description: set up MMC muxing
board/omap2420h4/omap2420h4.c:void muxSetupMMCSD(void)
board/omap2420h4/omap2420h4.c: /* SDMMC_CLKI pin configuration, PIN = H15
*/
board/omap2420h4/omap2420h4.c: MuxConfigReg = (volatile unsigned char
*)CONTROL_PADCONF_MMC_CLKI,
board/omap2420h4/omap2420h4.c: /* SDMMC_CLKO pin configuration, PIN = G19
*/
board/omap2420h4/omap2420h4.c: MuxConfigReg = (volatile unsigned char
*)CONTROL_PADCONF_MMC_CLKO,
board/omap2420h4/omap2420h4.c: /* SDMMC_CMD pin configuration, PIN = H18
*/
board/omap2420h4/omap2420h4.c: MuxConfigReg = (volatile unsigned char
*)CONTROL_PADCONF_MMC_CMD,
board/omap2420h4/omap2420h4.c: /* SDMMC_DAT0 pin configuration, PIN = F20
*/
board/omap2420h4/omap2420h4.c: MuxConfigReg = (volatile unsigned char
*)CONTROL_PADCONF_MMC_DAT0,
board/omap2420h4/omap2420h4.c: /* SDMMC_DAT1 pin configuration, PIN = H14
*/
board/omap2420h4/omap2420h4.c: MuxConfigReg = (volatile unsigned char
*)CONTROL_PADCONF_MMC_DAT1,
board/omap2420h4/omap2420h4.c: /* SDMMC_DAT2 pin configuration, PIN = E19
*/
board/omap2420h4/omap2420h4.c: MuxConfigReg = (volatile unsigned char
*)CONTROL_PADCONF_MMC_DAT2,
board/omap2420h4/omap2420h4.c: /* SDMMC_DAT3 pin configuration, PIN = D19
*/
board/omap2420h4/omap2420h4.c: MuxConfigReg = (volatile unsigned char
*)CONTROL_PADCONF_MMC_DAT3,
board/omap2420h4/omap2420h4.c: /* SDMMC_DDIR0 pin configuration, PIN = F19
*/
board/omap2420h4/omap2420h4.c: MuxConfigReg = (volatile unsigned char
*)CONTROL_PADCONF_MMC_DAT_DIR0,
board/omap2420h4/omap2420h4.c: /* SDMMC_DDIR1 pin configuration, PIN = E20
*/
board/omap2420h4/omap2420h4.c: MuxConfigReg = (volatile unsigned char
*)CONTROL_PADCONF_MMC_DAT_DIR1,
board/omap2420h4/omap2420h4.c: /* SDMMC_DDIR2 pin configuration, PIN = F18
*/
board/omap2420h4/omap2420h4.c: MuxConfigReg = (volatile unsigned char
*)CONTROL_PADCONF_MMC_DAT_DIR2,
board/omap2420h4/omap2420h4.c: /* SDMMC_DDIR3 pin configuration, PIN = E18
*/
board/omap2420h4/omap2420h4.c: MuxConfigReg = (volatile unsigned char
*)CONTROL_PADCONF_MMC_DAT_DIR3,
board/omap2420h4/omap2420h4.c: /* SDMMC_CDIR pin configuration, PIN = G18
*/
board/omap2420h4/omap2420h4.c: MuxConfigReg = (volatile unsigned char
*)CONTROL_PADCONF_MMC_CMD_DIR,
board/omap2420h4/omap2420h4.c: /* MMC_CD pin configuration, PIN =
3 ---2420IP ONLY---*/
board/omap2420h4/omap2420h4.c: /* MMC_CD for 2422IP=K1 */
board/omap2420h4/omap2420h4.c: /* MMC_WP pin configuration, PIN = B4
*/
board/omap2420h4/omap2420h4.c: /* PIN = M18 GPIO.96->MMC2_WP mode
-DO- */
board/omap2420h4/omap2420h4.c: /* PIN = M18 GPIO.96->MMC2_WP mode
-DO- */
board/omap2420h4/omap2420h4.c: /* PIN = B3, GPIO.0->MMC_CD, mode 3,
set above */
board/omap5912osk/omap5912osk.c: /* mux setup for SD/MMC driver */
board/omap5912osk/omap5912osk.c: /* bit 13 for MMC2 XOR_CLK */
board/omap5912osk/omap5912osk.c: /*2.75V for MMCSDIO1 */
board/omap5912osk/omap5912osk.c: /* PullUps for SD/MMC driver */
board/sc520_cdp/sc520_cdp_asm.S: movl $0xfffef000,%edi /* MMCR base
to edi */
board/sc520_cdp/sc520_cdp_asm.S: movw 2(%esi), %dx /* load MMCR
offset to dx */
board/sc520_cdp/sc520_cdp_asm16.S: /* Alias MMCR to 0xdf000 */
board/sc520_cdp/sc520_cdp_asm16.S: /* Set ds to point to MMCR alias */
board/sc520_cdp/sc520_cdp_asm16.S: /* Disabe MMCR alias */
board/sc520_cdp/sc520_cdp_asm16.S: /* Alias MMCR to 0xdf000 */
board/sc520_cdp/sc520_cdp_asm16.S: /* Set ds to point to MMCR alias */
board/sc520_cdp/sc520_cdp_asm16.S: /* issue software reset thorugh MMCR */
board/sc520_spunk/sc520_spunk_asm.S: movl $0xfffef000,%edi /* MMCR
base to edi */
board/sc520_spunk/sc520_spunk_asm.S: movw 2(%esi), %dx /* load MMCR
offset to dx */
board/sc520_spunk/sc520_spunk_asm16.S: /* Alias MMCR to 0xdf000 */
board/sc520_spunk/sc520_spunk_asm16.S: /* Set ds to point to MMCR alias */
board/sc520_spunk/sc520_spunk_asm16.S: /* Disabe MMCR alias */
board/sc520_spunk/sc520_spunk_asm16.S: /* Alias MMCR to 0xdf000 */
board/sc520_spunk/sc520_spunk_asm16.S: /* Set ds to point to MMCR alias */
board/sc520_spunk/sc520_spunk_asm16.S: /* issue software reset thorugh MMCR
*/
CHANGELOG: * support for USB/MMC devices is missing in #if line
CHANGELOG: - Add command support for MMC
CHANGELOG: - Add Intel PXA support for MMC
CHANGELOG: - Enable MMC and FAT for lubbock board
common/cmd_ext2.c:#if defined(CONFIG_MMC)
common/cmd_fat.c:#if defined(CONFIG_MMC)
common/cmd_mem.c:#if (CONFIG_COMMANDS & CFG_CMD_MMC)
common/cmd_mem.c:#if (CONFIG_COMMANDS & CFG_CMD_MMC)
common/cmd_mem.c: puts ("Copy to MMC... ");
common/cmd_mem.c: puts ("Copy from MMC... ");
common/cmd_mmc.c:#if (CONFIG_COMMANDS & CFG_CMD_MMC)
common/cmd_mmc.c: printf ("No MMC card found\n");
common/cmd_mmc.c:#endif /* CFG_CMD_MMC */
common/cmd_reiser.c:#if defined(CONFIG_MMC)
cpu/pxa/mmc.c:#ifdef CONFIG_MMC
cpu/pxa/mmc.c:static uchar mmc_buf[MMC_BLOCK_SIZE];
cpu/pxa/mmc.c: MMC_STRPCL = MMC_STRPCL_STOP_CLK;
cpu/pxa/mmc.c: MMC_I_MASK = ~MMC_I_MASK_CLK_IS_OFF;
cpu/pxa/mmc.c: while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF));
cpu/pxa/mmc.c: MMC_CMD = cmd;
cpu/pxa/mmc.c: MMC_ARGH = argh;
cpu/pxa/mmc.c: MMC_ARGL = argl;
cpu/pxa/mmc.c: MMC_CMDAT = cmdat;
cpu/pxa/mmc.c: MMC_I_MASK = ~MMC_I_MASK_END_CMD_RES;
cpu/pxa/mmc.c: MMC_STRPCL = MMC_STRPCL_START_CLK;
cpu/pxa/mmc.c: while (!(MMC_I_REG & MMC_I_REG_END_CMD_RES));
cpu/pxa/mmc.c: status = MMC_STAT;
cpu/pxa/mmc.c: debug("MMC status %x\n", status);
cpu/pxa/mmc.c: if (status & MMC_STAT_TIME_OUT_RESPONSE)
cpu/pxa/mmc.c: case MMC_CMDAT_R1:
cpu/pxa/mmc.c: case MMC_CMDAT_R3:
cpu/pxa/mmc.c: case MMC_CMDAT_R2:
cpu/pxa/mmc.c: ulong res_fifo = MMC_RES;
cpu/pxa/mmc.c:#ifdef MMC_DEBUG
cpu/pxa/mmc.c: printf("MMC resp[%d] = %02x\n", i, resp[i]);
cpu/pxa/mmc.c: printf("MMC resp[%d] = %02x\n", i+1, resp[i+1]);
cpu/pxa/mmc.c: resp = mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl,
MMC_CMDAT_R1);
cpu/pxa/mmc.c: MMC_STRPCL = MMC_STRPCL_STOP_CLK;
cpu/pxa/mmc.c: MMC_RDTO = 0xffff;
cpu/pxa/mmc.c: MMC_NOB = 1;
cpu/pxa/mmc.c: MMC_BLKLEN = len;
cpu/pxa/mmc.c: resp = mmc_cmd(MMC_CMD_READ_BLOCK, argh, argl,
cpu/pxa/mmc.c:
MMC_CMDAT_R1|MMC_CMDAT_READ|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN);
cpu/pxa/mmc.c: MMC_I_MASK = ~MMC_I_MASK_RXFIFO_RD_REQ;
cpu/pxa/mmc.c: if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ)
cpu/pxa/mmc.c: *dst++ = MMC_RXFIFO;
cpu/pxa/mmc.c: status = MMC_STAT;
cpu/pxa/mmc.c: if (status & MMC_STAT_ERRORS)
cpu/pxa/mmc.c: printf("MMC_STAT error %lx\n", status);
cpu/pxa/mmc.c: MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE;
cpu/pxa/mmc.c: while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE));
cpu/pxa/mmc.c: status = MMC_STAT;
cpu/pxa/mmc.c: if (status & MMC_STAT_ERRORS)
cpu/pxa/mmc.c: printf("MMC_STAT error %lx\n", status);
cpu/pxa/mmc.c: resp = mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl,
MMC_CMDAT_R1);
cpu/pxa/mmc.c: MMC_STRPCL = MMC_STRPCL_STOP_CLK;
cpu/pxa/mmc.c: MMC_NOB = 1;
cpu/pxa/mmc.c: MMC_BLKLEN = len;
cpu/pxa/mmc.c: resp = mmc_cmd(MMC_CMD_WRITE_BLOCK, argh, argl,
cpu/pxa/mmc.c:
MMC_CMDAT_R1|MMC_CMDAT_WRITE|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN);
cpu/pxa/mmc.c: MMC_I_MASK = ~MMC_I_MASK_TXFIFO_WR_REQ;
cpu/pxa/mmc.c: if (MMC_I_REG & MMC_I_REG_TXFIFO_WR_REQ)
cpu/pxa/mmc.c: MMC_TXFIFO = *src++;
cpu/pxa/mmc.c: MMC_PRTBUF = MMC_PRTBUF_BUF_PART_FULL;
cpu/pxa/mmc.c: status = MMC_STAT;
cpu/pxa/mmc.c: if (status & MMC_STAT_ERRORS)
cpu/pxa/mmc.c: printf("MMC_STAT error %lx\n", status);
cpu/pxa/mmc.c: MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE;
cpu/pxa/mmc.c: while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE));
cpu/pxa/mmc.c: MMC_I_MASK = ~MMC_I_MASK_PRG_DONE;
cpu/pxa/mmc.c: while (!(MMC_I_REG & MMC_I_REG_PRG_DONE));
cpu/pxa/mmc.c: status = MMC_STAT;
cpu/pxa/mmc.c: if (status & MMC_STAT_ERRORS)
cpu/pxa/mmc.c: printf("MMC_STAT error %lx\n", status);
cpu/pxa/mmc.c: printf("Please initial the MMC first\n");
cpu/pxa/mmc.c: mmc_block_size = MMC_BLOCK_SIZE;
cpu/pxa/mmc.c: src -= CFG_MMC_BASE;
cpu/pxa/mmc.c: printf("Please initial the MMC first\n");
cpu/pxa/mmc.c: mmc_block_size = MMC_BLOCK_SIZE;
cpu/pxa/mmc.c: dst -= CFG_MMC_BASE;
cpu/pxa/mmc.c: int mmc_block_size = MMC_BLOCK_SIZE;
cpu/pxa/mmc.c: ulong src = blknr * mmc_block_size + CFG_MMC_BASE;
cpu/pxa/mmc.c: set_GPIO_mode( GPIO6_MMCCLK_MD );
cpu/pxa/mmc.c: set_GPIO_mode( GPIO8_MMCCS0_MD );
cpu/pxa/mmc.c: CKEN |= CKEN12_MMC; /* enable MMC unit clock */
cpu/pxa/mmc.c: MMC_CLKRT = MMC_CLKRT_0_3125MHZ;
cpu/pxa/mmc.c: MMC_RESTO = MMC_RES_TO_MAX;
cpu/pxa/mmc.c: MMC_SPI = MMC_SPI_DISABLE;
cpu/pxa/mmc.c: resp = mmc_cmd(1, 0x00ff, 0xc000,
MMC_CMDAT_INIT|MMC_CMDAT_BUSY|MMC_CMDAT_R3);
cpu/pxa/mmc.c: resp = mmc_cmd(1, 0x00ff, 0xff00,
MMC_CMDAT_BUSY|MMC_CMDAT_R3);
cpu/pxa/mmc.c: resp = mmc_cmd(2, 0, 0, MMC_CMDAT_R2);
cpu/pxa/mmc.c: printf("MMC found. Card desciption is:\n");
cpu/pxa/mmc.c: mmc_dev.if_type = IF_TYPE_MMC;
cpu/pxa/mmc.c: /* MMC exists, get CSD too */
cpu/pxa/mmc.c: resp = mmc_cmd(MMC_CMD_SET_RCA, MMC_DEFAULT_RCA, 0,
MMC_CMDAT_R1);
cpu/pxa/mmc.c: resp = mmc_cmd(MMC_CMD_SEND_CSD, MMC_DEFAULT_RCA, 0,
MMC_CMDAT_R2);
cpu/pxa/mmc.c: MMC_CLKRT = 0; /* 20 MHz */
cpu/pxa/mmc.c: resp = mmc_cmd(7, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1);
cpu/pxa/mmc.c: if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0x02000000)
disk/part.c: defined(CONFIG_MMC) || \
disk/part.c:#endif /* CFG_CMD_IDE || CFG_CMD_SCSI || CFG_CMD_USB ||
CONFIG_MMC */
disk/part_amiga.c: defined(CONFIG_MMC) || \
disk/part_dos.c: defined(CONFIG_MMC) || \
disk/part_iso.c: defined(CONFIG_MMC) || \
disk/part_mac.c: defined(CONFIG_MMC) || \
doc/TODO-i386:* SC520 MMCR reset
fs/fat/fat.c: (CONFIG_COMMANDS & CFG_CMD_USB) || (CONFIG_MMC)
fs/fat/fat.c: case IF_TYPE_MMC : printf("MMC"); break;
include/asm-arm/arch-arm1136/mux.h:void muxSetupMMCSD(void) ;
include/asm-arm/arch-arm1136/mux.h:/* Pin Muxing registers used for MMCSD */
include/asm-arm/arch-arm1136/mux.h:#define CONTROL_PADCONF_MMC_CLKI
((volatile unsigned char *)0x480000FE)
include/asm-arm/arch-arm1136/mux.h:#define CONTROL_PADCONF_MMC_CLKO
((volatile unsigned char *)0x480000F3)
include/asm-arm/arch-arm1136/mux.h:#define CONTROL_PADCONF_MMC_CMD
((volatile unsigned char *)0x480000F4)
include/asm-arm/arch-arm1136/mux.h:#define CONTROL_PADCONF_MMC_DAT0
((volatile unsigned char *)0x480000F5)
include/asm-arm/arch-arm1136/mux.h:#define CONTROL_PADCONF_MMC_DAT1
((volatile unsigned char *)0x480000F6)
include/asm-arm/arch-arm1136/mux.h:#define CONTROL_PADCONF_MMC_DAT2
((volatile unsigned char *)0x480000F7)
include/asm-arm/arch-arm1136/mux.h:#define CONTROL_PADCONF_MMC_DAT3
((volatile unsigned char *)0x480000F8)
include/asm-arm/arch-arm1136/mux.h:#define CONTROL_PADCONF_MMC_DAT_DIR0
((volatile unsigned char *)0x480000F9)
include/asm-arm/arch-arm1136/mux.h:#define CONTROL_PADCONF_MMC_DAT_DIR1
((volatile unsigned char *)0x480000FA)
include/asm-arm/arch-arm1136/mux.h:#define CONTROL_PADCONF_MMC_DAT_DIR2
((volatile unsigned char *)0x480000FB)
include/asm-arm/arch-arm1136/mux.h:#define CONTROL_PADCONF_MMC_DAT_DIR3
((volatile unsigned char *)0x480000FC)
include/asm-arm/arch-arm1136/mux.h:#define CONTROL_PADCONF_MMC_CMD_DIR
((volatile unsigned char *)0x480000FD)
include/asm-arm/arch-arm920t/imx-regs.h:#define IMX_MMC_BASE
(0x14000 + IMX_IO_BASE)
include/asm-arm/arch-pxa/mmc.h:#ifndef __MMC_PXA_P_H__
include/asm-arm/arch-pxa/mmc.h:#define __MMC_PXA_P_H__
include/asm-arm/arch-pxa/mmc.h:/* PXA-250 MMC controller registers */
include/asm-arm/arch-pxa/mmc.h:/* MMC_STRPCL */
include/asm-arm/arch-pxa/mmc.h:#define MMC_STRPCL_STOP_CLK (0x0001UL)
include/asm-arm/arch-pxa/mmc.h:#define MMC_STRPCL_START_CLK (0x0002UL)
include/asm-arm/arch-pxa/mmc.h:/* MMC_STAT */
include/asm-arm/arch-pxa/mmc.h:#define MMC_STAT_END_CMD_RES (0x0001UL <<
13)
include/asm-arm/arch-pxa/mmc.h:#define MMC_STAT_PRG_DONE (0x0001UL <<
12)
include/asm-arm/arch-pxa/mmc.h:#define MMC_STAT_DATA_TRAN_DONE
(0x0001UL << 11)
include/asm-arm/arch-pxa/mmc.h:#define MMC_STAT_CLK_EN (0x0001UL << 8)
include/asm-arm/arch-pxa/mmc.h:#define MMC_STAT_RECV_FIFO_FULL
(0x0001UL << 7)
include/asm-arm/arch-pxa/mmc.h:#define MMC_STAT_XMIT_FIFO_EMPTY
(0x0001UL << 6)
include/asm-arm/arch-pxa/mmc.h:#define MMC_STAT_RES_CRC_ERROR
(0x0001UL << 5)
include/asm-arm/arch-pxa/mmc.h:#define MMC_STAT_SPI_READ_ERROR_TOKEN
(0x0001UL << 4)
include/asm-arm/arch-pxa/mmc.h:#define MMC_STAT_CRC_READ_ERROR
(0x0001UL << 3)
include/asm-arm/arch-pxa/mmc.h:#define MMC_STAT_CRC_WRITE_ERROR
(0x0001UL << 2)
include/asm-arm/arch-pxa/mmc.h:#define MMC_STAT_TIME_OUT_RESPONSE
(0x0001UL << 1)
include/asm-arm/arch-pxa/mmc.h:#define MMC_STAT_READ_TIME_OUT
(0x0001UL)
include/asm-arm/arch-pxa/mmc.h:#define MMC_STAT_ERRORS
(MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\
include/asm-arm/arch-pxa/mmc.h:
|MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\
include/asm-arm/arch-pxa/mmc.h:
|MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR)
include/asm-arm/arch-pxa/mmc.h:/* MMC_CLKRT */
include/asm-arm/arch-pxa/mmc.h:#define MMC_CLKRT_20MHZ (0x0000UL)
include/asm-arm/arch-pxa/mmc.h:#define MMC_CLKRT_10MHZ (0x0001UL)
include/asm-arm/arch-pxa/mmc.h:#define MMC_CLKRT_5MHZ (0x0002UL)
include/asm-arm/arch-pxa/mmc.h:#define MMC_CLKRT_2_5MHZ (0x0003UL)
include/asm-arm/arch-pxa/mmc.h:#define MMC_CLKRT_1_25MHZ (0x0004UL)
include/asm-arm/arch-pxa/mmc.h:#define MMC_CLKRT_0_625MHZ (0x0005UL)
include/asm-arm/arch-pxa/mmc.h:#define MMC_CLKRT_0_3125MHZ (0x0006UL)
include/asm-arm/arch-pxa/mmc.h:/* MMC_SPI */
include/asm-arm/arch-pxa/mmc.h:#define MMC_SPI_DISABLE (0x00UL)
include/asm-arm/arch-pxa/mmc.h:#define MMC_SPI_EN (0x01UL)
include/asm-arm/arch-pxa/mmc.h:#define MMC_SPI_CS_EN (0x01UL << 2)
include/asm-arm/arch-pxa/mmc.h:#define MMC_SPI_CS_ADDRESS (0x01UL <<
3)
include/asm-arm/arch-pxa/mmc.h:#define MMC_SPI_CRC_ON (0x01UL << 1)
include/asm-arm/arch-pxa/mmc.h:/* MMC_CMDAT */
include/asm-arm/arch-pxa/mmc.h:#define MMC_CMDAT_MMC_DMA_EN (0x0001UL << 7)
include/asm-arm/arch-pxa/mmc.h:#define MMC_CMDAT_INIT (0x0001UL << 6)
include/asm-arm/arch-pxa/mmc.h:#define MMC_CMDAT_BUSY (0x0001UL << 5)
include/asm-arm/arch-pxa/mmc.h:#define MMC_CMDAT_STREAM (0x0001UL << 4)
include/asm-arm/arch-pxa/mmc.h:#define MMC_CMDAT_BLOCK (0x0000UL << 4)
include/asm-arm/arch-pxa/mmc.h:#define MMC_CMDAT_WRITE (0x0001UL << 3)
include/asm-arm/arch-pxa/mmc.h:#define MMC_CMDAT_READ (0x0000UL << 3)
include/asm-arm/arch-pxa/mmc.h:#define MMC_CMDAT_DATA_EN (0x0001UL <<
2)
include/asm-arm/arch-pxa/mmc.h:#define MMC_CMDAT_R1 (0x0001UL)
include/asm-arm/arch-pxa/mmc.h:#define MMC_CMDAT_R2 (0x0002UL)
include/asm-arm/arch-pxa/mmc.h:#define MMC_CMDAT_R3 (0x0003UL)
include/asm-arm/arch-pxa/mmc.h:/* MMC_RESTO */
include/asm-arm/arch-pxa/mmc.h:#define MMC_RES_TO_MAX (0x007fUL) /*
[6:0] */
include/asm-arm/arch-pxa/mmc.h:/* MMC_RDTO */
include/asm-arm/arch-pxa/mmc.h:#define MMC_READ_TO_MAX (0x0ffffUL) /*
[15:0] */
include/asm-arm/arch-pxa/mmc.h:/* MMC_BLKLEN */
include/asm-arm/arch-pxa/mmc.h:#define MMC_BLK_LEN_MAX (0x03ffUL) /*
[9:0] */
include/asm-arm/arch-pxa/mmc.h:/* MMC_PRTBUF */
include/asm-arm/arch-pxa/mmc.h:#define MMC_PRTBUF_BUF_PART_FULL
(0x01UL)
include/asm-arm/arch-pxa/mmc.h:#define MMC_PRTBUF_BUF_FULL (0x00UL )
include/asm-arm/arch-pxa/mmc.h:/* MMC_I_MASK */
include/asm-arm/arch-pxa/mmc.h:#define MMC_I_MASK_TXFIFO_WR_REQ (0x01UL <<
6)
include/asm-arm/arch-pxa/mmc.h:#define MMC_I_MASK_RXFIFO_RD_REQ (0x01UL <<
5)
include/asm-arm/arch-pxa/mmc.h:#define MMC_I_MASK_CLK_IS_OFF (0x01UL <<
4)
include/asm-arm/arch-pxa/mmc.h:#define MMC_I_MASK_STOP_CMD (0x01UL << 3)
include/asm-arm/arch-pxa/mmc.h:#define MMC_I_MASK_END_CMD_RES (0x01UL <<
2)
include/asm-arm/arch-pxa/mmc.h:#define MMC_I_MASK_PRG_DONE (0x01UL << 1)
include/asm-arm/arch-pxa/mmc.h:#define MMC_I_MASK_DATA_TRAN_DONE
(0x01UL)
include/asm-arm/arch-pxa/mmc.h:#define MMC_I_MASK_ALL (0x07fUL)
include/asm-arm/arch-pxa/mmc.h:/* MMC_I_REG */
include/asm-arm/arch-pxa/mmc.h:#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL
<< 6)
include/asm-arm/arch-pxa/mmc.h:#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL
<< 5)
include/asm-arm/arch-pxa/mmc.h:#define MMC_I_REG_CLK_IS_OFF (0x01UL << 4)
include/asm-arm/arch-pxa/mmc.h:#define MMC_I_REG_STOP_CMD (0x01UL <<
3)
include/asm-arm/arch-pxa/mmc.h:#define MMC_I_REG_END_CMD_RES (0x01UL
<< 2)
include/asm-arm/arch-pxa/mmc.h:#define MMC_I_REG_PRG_DONE (0x01UL <<
1)
include/asm-arm/arch-pxa/mmc.h:#define MMC_I_REG_DATA_TRAN_DONE (0x01UL)
include/asm-arm/arch-pxa/mmc.h:#define MMC_I_REG_ALL (0x007fUL)
include/asm-arm/arch-pxa/mmc.h:/* MMC_CMD */
include/asm-arm/arch-pxa/mmc.h:#define MMC_CMD_INDEX_MAX (0x006fUL)
/* [5:0] */
include/asm-arm/arch-pxa/mmc.h:#define MMC_DEFAULT_RCA 1
include/asm-arm/arch-pxa/mmc.h:#define MMC_BLOCK_SIZE 512
include/asm-arm/arch-pxa/mmc.h:#define MMC_CMD_RESET 0
include/asm-arm/arch-pxa/mmc.h:#define MMC_CMD_SEND_OP_COND 1
include/asm-arm/arch-pxa/mmc.h:#define MMC_CMD_ALL_SEND_CID 2
include/asm-arm/arch-pxa/mmc.h:#define MMC_CMD_SET_RCA 3
include/asm-arm/arch-pxa/mmc.h:#define MMC_CMD_SEND_CSD 9
include/asm-arm/arch-pxa/mmc.h:#define MMC_CMD_SEND_CID 10
include/asm-arm/arch-pxa/mmc.h:#define MMC_CMD_SEND_STATUS 13
include/asm-arm/arch-pxa/mmc.h:#define MMC_CMD_SET_BLOCKLEN 16
include/asm-arm/arch-pxa/mmc.h:#define MMC_CMD_READ_BLOCK 17
include/asm-arm/arch-pxa/mmc.h:#define MMC_CMD_RD_BLK_MULTI 18
include/asm-arm/arch-pxa/mmc.h:#define MMC_CMD_WRITE_BLOCK 24
include/asm-arm/arch-pxa/mmc.h:#define MMC_MAX_BLOCK_SIZE 512
include/asm-arm/arch-pxa/mmc.h:#define MMC_R1_IDLE_STATE 0x01
include/asm-arm/arch-pxa/mmc.h:#define MMC_R1_ERASE_STATE 0x02
include/asm-arm/arch-pxa/mmc.h:#define MMC_R1_ILLEGAL_CMD 0x04
include/asm-arm/arch-pxa/mmc.h:#define MMC_R1_COM_CRC_ERR 0x08
include/asm-arm/arch-pxa/mmc.h:#define MMC_R1_ERASE_SEQ_ERR 0x01
include/asm-arm/arch-pxa/mmc.h:#define MMC_R1_ADDR_ERR 0x02
include/asm-arm/arch-pxa/mmc.h:#define MMC_R1_PARAM_ERR 0x04
include/asm-arm/arch-pxa/mmc.h:#define MMC_R1B_WP_ERASE_SKIP 0x0002
include/asm-arm/arch-pxa/mmc.h:#define MMC_R1B_ERR 0x0004
include/asm-arm/arch-pxa/mmc.h:#define MMC_R1B_CC_ERR 0x0008
include/asm-arm/arch-pxa/mmc.h:#define MMC_R1B_CARD_ECC_ERR 0x0010
include/asm-arm/arch-pxa/mmc.h:#define MMC_R1B_WP_VIOLATION 0x0020
include/asm-arm/arch-pxa/mmc.h:#define MMC_R1B_ERASE_PARAM 0x0040
include/asm-arm/arch-pxa/mmc.h:#define MMC_R1B_OOR 0x0080
include/asm-arm/arch-pxa/mmc.h:#define MMC_R1B_IDLE_STATE 0x0100
include/asm-arm/arch-pxa/mmc.h:#define MMC_R1B_ERASE_RESET 0x0200
include/asm-arm/arch-pxa/mmc.h:#define MMC_R1B_ILLEGAL_CMD 0x0400
include/asm-arm/arch-pxa/mmc.h:#define MMC_R1B_COM_CRC_ERR 0x0800
include/asm-arm/arch-pxa/mmc.h:#define MMC_R1B_ERASE_SEQ_ERR 0x1000
include/asm-arm/arch-pxa/mmc.h:#define MMC_R1B_ADDR_ERR 0x2000
include/asm-arm/arch-pxa/mmc.h:#define MMC_R1B_PARAM_ERR 0x4000
include/asm-arm/arch-pxa/mmc.h:#endif /* __MMC_PXA_P_H__ */
include/asm-arm/arch-pxa/pxa-regs.h:#define DRCMR21 __REG(0x40000154) /*
Request to Channel Map Register for MMC receive Request */
include/asm-arm/arch-pxa/pxa-regs.h:#define DRCMR22 __REG(0x40000158) /*
Request to Channel Map Register for MMC transmit Request */
include/asm-arm/arch-pxa/pxa-regs.h:#define DRCMRRXMMC DRCMR21
include/asm-arm/arch-pxa/pxa-regs.h:#define DRCMRTXMMC DRCMR22
include/asm-arm/arch-pxa/pxa-regs.h:#define GPIO6_MMCCLK 6 /* MMC Clock */
include/asm-arm/arch-pxa/pxa-regs.h:#define GPIO8_MMCCS0 8 /* MMC Chip
Select 0 */
include/asm-arm/arch-pxa/pxa-regs.h:#define GPIO9_MMCCS1 9 /* MMC Chip
Select 1 */
include/asm-arm/arch-pxa/pxa-regs.h:#define GPIO34_MMCCS0 34 /* MMC Chip
Select 0 */
include/asm-arm/arch-pxa/pxa-regs.h:#define GPIO39_MMCCS1 39 /* MMC Chip
Select 1 */
include/asm-arm/arch-pxa/pxa-regs.h:#define GPIO53_MMCCLK 53 /* MMC Clock
*/
include/asm-arm/arch-pxa/pxa-regs.h:#define GPIO54_MMCCLK 54 /* MMC Clock
*/
include/asm-arm/arch-pxa/pxa-regs.h:#define GPIO67_MMCCS0 67 /* MMC Chip
Select 0 */
include/asm-arm/arch-pxa/pxa-regs.h:#define GPIO68_MMCCS1 68 /* MMC Chip
Select 1 */
include/asm-arm/arch-pxa/pxa-regs.h:#define GPIO69_MMCCLK 69 /* MMC_CLK */
include/asm-arm/arch-pxa/pxa-regs.h:#define GPIO6_MMCCLK_MD ( 6 |
GPIO_ALT_FN_1_OUT)
include/asm-arm/arch-pxa/pxa-regs.h:#define GPIO8_MMCCS0_MD ( 8 |
GPIO_ALT_FN_1_OUT)
include/asm-arm/arch-pxa/pxa-regs.h:#define GPIO9_MMCCS1_MD ( 9 |
GPIO_ALT_FN_1_OUT)
include/asm-arm/arch-pxa/pxa-regs.h:#define GPIO34_MMCCS0_MD (34 |
GPIO_ALT_FN_2_OUT)
include/asm-arm/arch-pxa/pxa-regs.h:#define GPIO39_MMCCS1_MD (39 |
GPIO_ALT_FN_1_OUT)
include/asm-arm/arch-pxa/pxa-regs.h:#define GPIO53_MMCCLK_MD (53 |
GPIO_ALT_FN_1_OUT)
include/asm-arm/arch-pxa/pxa-regs.h:#define GPIO54_MMCCLK_MD (54 |
GPIO_ALT_FN_1_OUT)
include/asm-arm/arch-pxa/pxa-regs.h:#define GPIO67_MMCCS0_MD (67 |
GPIO_ALT_FN_1_OUT)
include/asm-arm/arch-pxa/pxa-regs.h:#define GPIO68_MMCCS1_MD (68 |
GPIO_ALT_FN_1_OUT)
include/asm-arm/arch-pxa/pxa-regs.h:#define GPIO69_MMCCLK_MD (69 |
GPIO_ALT_FN_1_OUT)
include/asm-arm/arch-pxa/pxa-regs.h: * MultiMediaCard (MMC) controller
include/asm-arm/arch-pxa/pxa-regs.h:#define MMC_STRPCL __REG(0x41100000) /*
Control to start and stop MMC clock */
include/asm-arm/arch-pxa/pxa-regs.h:#define MMC_STAT __REG(0x41100004) /*
MMC Status Register (read only) */
include/asm-arm/arch-pxa/pxa-regs.h:#define MMC_CLKRT __REG(0x41100008) /*
MMC clock rate */
include/asm-arm/arch-pxa/pxa-regs.h:#define MMC_SPI __REG(0x4110000c) /*
SPI mode control bits */
include/asm-arm/arch-pxa/pxa-regs.h:#define MMC_CMDAT __REG(0x41100010) /*
Command/response/data sequence control */
include/asm-arm/arch-pxa/pxa-regs.h:#define MMC_RESTO __REG(0x41100014) /*
Expected response time out */
include/asm-arm/arch-pxa/pxa-regs.h:#define MMC_RDTO __REG(0x41100018) /*
Expected data read time out */
include/asm-arm/arch-pxa/pxa-regs.h:#define MMC_BLKLEN __REG(0x4110001c) /*
Block length of data transaction */
include/asm-arm/arch-pxa/pxa-regs.h:#define MMC_NOB __REG(0x41100020) /*
Number of blocks, for block mode */
include/asm-arm/arch-pxa/pxa-regs.h:#define MMC_PRTBUF __REG(0x41100024) /*
Partial MMC_TXFIFO FIFO written */
include/asm-arm/arch-pxa/pxa-regs.h:#define MMC_I_MASK __REG(0x41100028) /*
Interrupt Mask */
include/asm-arm/arch-pxa/pxa-regs.h:#define MMC_I_REG __REG(0x4110002c) /*
Interrupt Register (read only) */
include/asm-arm/arch-pxa/pxa-regs.h:#define MMC_CMD __REG(0x41100030) /*
Index of current command */
include/asm-arm/arch-pxa/pxa-regs.h:#define MMC_ARGH __REG(0x41100034) /*
MSW part of the current command argument */
include/asm-arm/arch-pxa/pxa-regs.h:#define MMC_ARGL __REG(0x41100038) /*
LSW part of the current command argument */
include/asm-arm/arch-pxa/pxa-regs.h:#define MMC_RES __REG(0x4110003c) /*
Response FIFO (read only) */
include/asm-arm/arch-pxa/pxa-regs.h:#define MMC_RXFIFO __REG(0x41100040) /*
Receive FIFO (read only) */
include/asm-arm/arch-pxa/pxa-regs.h:#define MMC_TXFIFO __REG(0x41100044) /*
Transmit FIFO (write only) */
include/asm-arm/arch-pxa/pxa-regs.h:#define CKEN12_MMC (1 << 12) /* MMC Unit
Clock Enable */
include/cmd_confdefs.h:#define CFG_CMD_MMC 0x0008000000000000ULL /* MMC
support */
include/cmd_confdefs.h: CFG_CMD_MMC | \
include/lh7a400.h:#define DMA_MMCTX_OFFSET (0x080)
include/lh7a400.h:#define DMA_MMCRX_OFFSET (0x0C0)
include/lh7a400.h:#define LH7A400_DMA_MMCTX \
include/lh7a400.h: ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE +
DMA_MMCTX_OFFSET))
include/lh7a400.h:#define LH7A400_DMA_MMCRX \
include/lh7a400.h: ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE +
DMA_MMCRX_OFFSET))
include/mmc.h:#ifndef _MMC_H_
include/mmc.h:#define _MMC_H_
include/mmc.h:#endif /* _MMC_H_ */
include/part.h:#define IF_TYPE_MMC 6
include/s3c2400.h:#define S3C2400_MMC_BASE 0x15A00000
include/s3c2400.h:static inline S3C2400_MMC * const
S3C2400_GetBase_MMC(void)
include/s3c2400.h: return (S3C2400_MMC * const)S3C2400_MMC_BASE;
include/s3c2400.h:/* MMC INTERFACE */
include/s3c2400.h:#define rMMCON (*(volatile unsigned *)0x15a00000)
include/s3c2400.h:#define rMMCRR (*(volatile unsigned *)0x15a00004)
include/s3c2400.h:#define rMMCR7 (*(volatile unsigned *)0x15a0001C)
include/s3c2400.h:#define rMMCMD0 (*(volatile unsigned *)0x15a00030)
include/s3c2400.h:#define rMMCMD1 (*(volatile unsigned *)0x15a00034)
include/s3c2400.h:#define rMMCR16 (*(volatile unsigned *)0x15a00038)
include/s3c2400.h:#define pISR_MMC (*(unsigned *)(_ISR_STARTADDRESS+0x74))
include/s3c2400.h:#define BIT_MMC (0x1<<21)
include/s3c24x0.h:/* MMC INTERFACE (see S3C2400 manual chapter 19) */
include/s3c24x0.h: S3C24X0_REG8 MMCON;
include/s3c24x0.h: S3C24X0_REG8 MMCRR;
include/s3c24x0.h: S3C24X0_REG8 MMCR7;
include/s3c24x0.h: S3C24X0_REG8 MMCMD0;
include/s3c24x0.h: S3C24X0_REG32 MMCMD1;
include/s3c24x0.h: S3C24X0_REG16 MMCR16;
include/s3c24x0.h: S3C24X0_REG8 MMCON;
include/s3c24x0.h: S3C24X0_REG8 MMCRR;
include/s3c24x0.h: S3C24X0_REG8 MMCR7;
include/s3c24x0.h: S3C24X0_REG8 MMCMD0;
include/s3c24x0.h: S3C24X0_REG32 MMCMD1;
include/s3c24x0.h: S3C24X0_REG16 MMCR16;
include/s3c24x0.h:} /*__attribute__((__packed__))*/ S3C2400_MMC;
include/asm-i386/ic/sc520.h:/* Memory mapped configuration registers, MMCR
*/
include/asm-i386/ic/sc520.h:/* MMCR Register bits (not all of them :) ) */
include/asm-ppc/processor.h:#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control
Register 0 */
include/asm-ppc/processor.h:#define SPRN_MMCR1 0x3BC /* Monitor Mode Control
Register 1 */
include/asm-ppc/processor.h:#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode
Control Register 0 */
include/asm-ppc/processor.h:#define SPRN_UMMCR1 0x3AC /* User Monitor Mode
Control Register 0 */
include/configs/ADNPESC1.h: CFG_CMD_MMC | \
include/configs/DK1C20.h: CFG_CMD_MMC | \
include/configs/DK1S10.h: CFG_CMD_MMC | \
include/configs/LANTEC.h: & ~CFG_CMD_MMC \
include/configs/MPC8260ADS.h: CFG_CMD_MMC | \
include/configs/MPC8266ADS.h: CFG_CMD_MMC | \
include/configs/RBC823.h: ~CFG_CMD_MMC & \
include/configs/ep8260.h: CFG_CMD_MMC | \
include/configs/hymod.h: CFG_CMD_MMC | \
include/configs/lubbock.h:#define CONFIG_MMC 1
include/configs/lubbock.h:#define CONFIG_COMMANDS (CONFIG_CMD_DFL |
CFG_CMD_MMC | CFG_CMD_FAT)
include/configs/lubbock.h:#define CFG_MMC_BASE 0xF0000000
include/configs/omap1510.h: * MMC/SD Host Controller Registers
include/configs/omap1510.h:#define OMAP_MMC_CMD 0xFFFB7800 /* MMC Command
*/
include/configs/omap1510.h:#define OMAP_MMC_ARGL 0xFFFB7804 /* MMC argument
low */
include/configs/omap1510.h:#define OMAP_MMC_ARGH 0xFFFB7808 /* MMC argument
high */
include/configs/omap1510.h:#define OMAP_MMC_CON 0xFFFB780C /* MMC system
configuration */
include/configs/omap1510.h:#define OMAP_MMC_STAT 0xFFFB7810 /* MMC status
*/
include/configs/omap1510.h:#define OMAP_MMC_IE 0xFFFB7814 /* MMC system
interrupt enable */
include/configs/omap1510.h:#define OMAP_MMC_CTO 0xFFFB7818 /* MMC command
time-out */
include/configs/omap1510.h:#define OMAP_MMC_DTO 0xFFFB781C /* MMC data
time-out */
include/configs/omap1510.h:#define OMAP_MMC_DATA 0xFFFB7820 /* MMC TX/RX
FIFO data */
include/configs/omap1510.h:#define OMAP_MMC_BLEN 0xFFFB7824 /* MMC block
length */
include/configs/omap1510.h:#define OMAP_MMC_NBLK 0xFFFB7828 /* MMC number
of blocks */
include/configs/omap1510.h:#define OMAP_MMC_BUF 0xFFFB782C /* MMC buffer
configuration */
include/configs/omap1510.h:#define OMAP_MMC_SPI 0xFFFB7830 /* MMC serial
port interface */
include/configs/omap1510.h:#define OMAP_MMC_SDIO 0xFFFB7834 /* MMC SDIO
mode configuration */
include/configs/omap1510.h:#define OMAP_MMC_SYST 0xFFFB7838 /* MMC system
test */
include/configs/omap1510.h:#define OMAP_MMC_REV 0xFFFB783C /* MMC module
version */
include/configs/omap1510.h:#define OMAP_MMC_RSP0 0xFFFB7840 /* MMC command
response 0 */
include/configs/omap1510.h:#define OMAP_MMC_RSP1 0xFFFB7844 /* MMC command
response 1 */
include/configs/omap1510.h:#define OMAP_MMC_RSP2 0xFFFB7848 /* MMC command
response 2 */
include/configs/omap1510.h:#define OMAP_MMC_RSP3 0xFFFB784C /* MMC command
response 3 */
include/configs/omap1510.h:#define OMAP_MMC_RSP4 0xFFFB7850 /* MMC command
response 4 */
include/configs/omap1510.h:#define OMAP_MMC_RSP5 0xFFFB7854 /* MMC command
response 5 */
include/configs/omap1510.h:#define OMAP_MMC_RSP6 0xFFFB7858 /* MMC command
response 6 */
include/configs/omap1510.h:#define OMAP_MMC_RSP7 0xFFFB785C /* MMC command
response 4 */
include/configs/omap1510.h:/* MMC masks */
include/configs/omap1510.h:#define OMAP_MMC_END_OF_CMD (1 << 0) /* End of
command phase */
include/configs/omap1510.h:#define OMAP_MMC_CARD_BUSY (1 << 2) /* Card enter
busy state */
include/configs/omap1510.h:#define OMAP_MMC_BLOCK_RS (1 << 3) /* Block
received/sent */
include/configs/omap1510.h:#define OMAP_MMC_EOF_BUSY (1 << 4) /* Card exit
busy state */
include/configs/omap1510.h:#define OMAP_MMC_DATA_TIMEOUT (1 << 5) /* Data
response time-out */
include/configs/omap1510.h:#define OMAP_MMC_DATA_CRC (1 << 6) /* Date CRC
error */
include/configs/omap1510.h:#define OMAP_MMC_CMD_TIMEOUT (1 << 7) /* Command
response time-out */
include/configs/omap1510.h:#define OMAP_MMC_CMD_CRC (1 << 8) /* Command CRC
error */
include/configs/omap1510.h:#define OMAP_MMC_A_FULL (1 << 10) /* Buffer
almost full */
include/configs/omap1510.h:#define OMAP_MMC_A_EMPTY (1 << 11) /* Buffer
almost empty */
include/configs/omap1510.h:#define OMAP_MMC_OCR_BUSY (1 << 12) /* OCR busy
*/
include/configs/omap1510.h:#define OMAP_MMC_CARD_IRQ (1 << 13) /* Card IRQ
received */
include/configs/omap1510.h:#define OMAP_MMC_CARD_ERR (1 << 14) /* Card
status error in response */
include/configs/omap2420h4.h:/* I'd like to get to these. Snap kernel loads
if we make MMC go */
include/configs/omap2420h4.h: /* #define CONFIG_COMMANDS
(CONFIG_CMD_DFL | CFG_CMD_NAND | CFG_CMD_JFFS2 | CFG_CMD_DHCP | CFG_CMD_MMC
| CFG_CMD_FAT | CFG_CMD_I2C) */
include/configs/pleb2.h:#undef CONFIG_MMC
include/configs/sc520_cdp.h:#undef CFG_RESET_SC520 /* use
SC520 MMCR's to reset cpu */
include/configs/sc520_spunk.h:#undef CFG_RESET_SC520 /* use
SC520 MMCR's to reset cpu */
include/configs/xsengine.h:#define CONFIG_MMC 1
include/configs/xsengine.h:#define CONFIG_COMMANDS (CONFIG_CMD_DFL |
CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_PING | CFG_CMD_JFFS2)
include/configs/xsengine.h:#define CFG_MMC_BASE 0xF0000000
include/pcmcia/ti113x.h:#define TI1250_MMC_ZVOUTEN 0x80
include/pcmcia/ti113x.h:#define TI1250_MMC_PORTSEL 0x40
include/pcmcia/ti113x.h:#define TI1250_MMC_ZVEN1 0x02
include/pcmcia/ti113x.h:#define TI1250_MMC_ZVEN0 0x01
README: CFG_CMD_MMC * MMC memory mapped support
README:- MMC Support:
README: The MMC controller on the Intel PXA is supported. To
README: enable this define CONFIG_MMC. The MMC can be
README: enabled with CFG_CMD_MMC. The MMC driver also works with
Don't view any suport MultiMediaCards in CVS version u-boot for AT91RM9200.
Absent.
Best Regards,
Dmitriy Cherkashin.
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