[U-Boot-Users] Using DCACHE instead of internal SRAM as the initial stack on PPC440GP?

[Shawn Jin]

> > (gdb) mon tlb 0 8
> >  0 : 00 f0000000 256MB V0 -> 1_f0000000 U:0000 -I-G- XWRXWR
> >  1 : 00 e0000000 256MB V0 -> 1_40000000 U:0000 -I-G- -WR-WR
> >  2 : 00 40000000   4KB V0 -> 1_4f000000 U:0000 ----- XWRXWR
> 
> Tlb 1 and 2 seem to overlap in the physical addresses!

Now I changed the page size to 4K in tlb 1. Here is the new tlb.

Core#0>tlb 0 8
 0 : 00 f0000000 256MB V0 -> 1_f0000000 U:0000 -I-G- XWRXWR
 1 : 00 e0000000   4KB V0 -> 1_40000000 U:0000 -I-G- -WR-WR
 2 : 00 40000000   4KB V0 -> 1_4f000000 U:0000 ----- XWRXWR
 3 : 00 00000000 256MB V0 -> 0_00000000 U:0000 -I-G- XWRXWR
 4 : 00 d0000000 256MB V0 -> 2_00000000 U:0000 -I-G- -WR-WR
 5 : 00 80000000 256MB V0 -> 3_00000000 U:0000 -I-G- -WR-WR
 6 : 00 00000000   1KB -0 -> 0_00000000 U:0000 ----- ------

> >       addi    r4, 0, PBxCR
> >       mtdcr   ebccfga, r4
> >       lis     r4, 0x4F01              /* BAS=0x4F0, BS=000 (1MB) */
> >       ori     r4, r4, 0xE000  /* BU=11 (r/w), BW=11 (32 bits) */
> 
> You don't set BW to 11 but to 10. Please use 0x4f01f000 for the PBxCR value. I
                                                                      
           ^^^^^^^^^^^
You really meant 0x4f01a000, didn't you? (set BW to 10).

> don't think this is the cause for the problem, but it can't hurt to correct
> this.

This doesn't seem to be the cause of the problem. :(

> Did you take a look at the error reporting registers (for example EBC0_BEAR /
> EBC0_BESR)?

I checked both registers. They are all 0s. Here is the debugging
screen dump. PC 0xfff80180 is the first instruction of stwu.

	li	r0,0
	stwu	r0,-4(r1)
	stwu	r0,-4(r1)		/* Terminate call chain */


Core#0>ti
    Core number       : 0
    Core state        : debug mode
    Debug entry cause : single step
    Current PC        : 0xfff80180
    Current CR        : 0x22ffdff7
    Current MSR       : 0x00021000
    Current LR        : 0xfffff174
Core#0>rd ebc0_besr
ebc0_besr: 0x00000000  0
Core#0>ti
    Core number       : 0
    Core state        : debug mode
    Debug entry cause : single step
    Current PC        : 0x00001400
    Current CR        : 0x22ffdff7
    Current MSR       : 0x00021000
    Current LR        : 0xfffff174
Core#0>rd ebc0_besr
ebc0_besr: 0x00000000  0

Thanks,
-Shawn.