[U-Boot-Users] Can MPC processors boot though the IMMR is at 0x0 (default configuration)?

[Yuli Barcohen]

>>>>> Peter Asemann writes:

    Peter> I'm going to try booting u-boot on a custom MPC875 board.  It
    Peter> has flash at the boot memory bank (bank 0).  It has no
    Peter> circuit to pull up pin 7/8 of the MPC data bus at processor
    Peter> start, so (the manual says) the IMMR/the internal memory is
    Peter> configured to reside at 0x0.

    Peter> I think this causes the internal memory to shadow the boot
    Peter> flash, which should prevent the board from booting.

No, it does not. CS0 is initialised to allow access to any address in
entire 4GB address space so the boot flash (which should be 32-bit wide
to use the default configuration, BTW) can be accessed at any address
except zero which is shadowed by the IMMR. Since bit 1 of HRCW is zero,
interrupt vectors reside at 0xFFF00000 so there is no overlap with the
IMMR. If you burn the U-Boot at this address, it should work (it will
change the IMMR value to CFG_IMMR).

    Peter> At least the internal memory shadows the boot memory bank in
    Peter> the debugger.

Probably your debugger (incorrectly) initialises the memory controller
and causes the overlap.

    Peter> That's why I was planning to solder some circuit to the board
    Peter> to configure the internal memory to be somewhere else at
    Peter> startup.

    Peter> The board designer says he can't believe the MPC875 default
    Peter> configuration is like that boards which use it can't boot.

    Peter> So - does someone incidentally know something about MPC
    Peter> default configurations and if MPCs can boot though the IMMR
    Peter> is at 0x0?  And if they can't, why the IMMR is at 0x0 by
    Peter> default?

-- 
========================================================================
 Yuli Barcohen       | Phone +972-9-765-1788 |  Software Project Leader
 yuli at arabellasw.com | Fax   +972-9-765-7494 | Arabella Software, Israel
========================================================================