[U-Boot-Users] [Patch] MPC8548CDS Local Bus Initialization Update

[Jon Loeliger]

Wolfgang,

This patch for the MPC8548CDS board updates the settings
for some of the Local Bus Initialization.

Thanks,
jdl


* Patch by Jon Loeliger, 2005-05-26
    - For the 8548CDS:
	- Fix reporting of Local Bus clock speed
        - Set Local Bus PLL to a better value
        - Use IO voltage hack on TSEC 3 and 4


Index: board/cds/mpc8548cds/mpc8548cds.c
===================================================================
RCS file: /cm/vault/u-boot/u-boot/board/cds/mpc8548cds/mpc8548cds.c,v
retrieving revision 1.1.4.1
retrieving revision 1.1.4.3
diff -u -r1.1.4.1 -r1.1.4.3
--- board/cds/mpc8548cds/mpc8548cds.c	5 May 2005 21:13:30 -0000	1.1.4.1
+++ board/cds/mpc8548cds/mpc8548cds.c	19 May 2005 17:27:33 -0000	1.1.4.3
@@ -87,6 +87,12 @@
 	 */
 	local_bus_init ();
 
+
+	/*
+	 * Hack TSEC 3 and 4 IO voltages.
+	 */
+	gur->tsec34ioovcr = 0xe7e0;	/*  1110 0111 1110 0xxx */
+
 	return 0;
 }
 
@@ -144,39 +150,23 @@
 	uint clkdiv;
 	uint lbc_hz;
 	sys_info_t sysinfo;
-	uint temp_lbcdll;
-
-	/*
-	 * Errata LBC11.
-	 * Fix Local Bus clock glitch when DLL is enabled.
-	 *
-	 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
-	 * If localbus freq is > 133Mhz, DLL can be safely enabled.
-	 * Between 66 and 133, the DLL is enabled with an override workaround.
-	 */
 
 	get_sys_info(&sysinfo);
-	clkdiv = lbc->lcrr & 0x0f;
+	clkdiv = (lbc->lcrr & 0x0f) * 2;
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
-	if (lbc_hz < 66) {
-		lbc->lcrr |= 0x80000000;	/* DLL Bypass */
-
-	} else if (lbc_hz >= 133) {
-		lbc->lcrr &= (~0x80000000);		/* DLL Enabled */
+	gur->lbiuiplldcr1 = 0x00078080;
+	if (clkdiv == 16) {
+		gur->lbiuiplldcr0 = 0x7c0f1bf0;
+	} else if (clkdiv == 8) {
+		gur->lbiuiplldcr0 = 0x6c0f1bf0;
+	} else if (clkdiv == 4) {
+		gur->lbiuiplldcr0 = 0x5c0f1bf0;
+	}
 
-	} else {
-		lbc->lcrr &= (~0x8000000);	/* DLL Enabled */
-		udelay(200);
+	lbc->lcrr |= 0x00030000;
 
-		/*
-		 * Sample LBC DLL ctrl reg, upshift it to set the
-		 * override bits.
-		 */
-		temp_lbcdll = gur->lbcdllcr;
-		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
-		asm("sync;isync;msync");
-	}
+	asm("sync;isync;msync");
 }
 
 /*
Index: include/asm-ppc/immap_85xx.h
===================================================================
RCS file: /cm/vault/u-boot/u-boot/include/asm-ppc/immap_85xx.h,v
retrieving revision 1.1.1.1.4.5
retrieving revision 1.1.1.1.4.6
diff -u -r1.1.1.1.4.5 -r1.1.1.1.4.6
--- include/asm-ppc/immap_85xx.h	5 May 2005 15:06:33 -0000	1.1.1.1.4.5
+++ include/asm-ppc/immap_85xx.h	16 May 2005 18:14:07 -0000	1.1.1.1.4.6
@@ -1554,7 +1554,9 @@
 	uint	ddrdllcr;	/* 0xe0e10 - DDR DLL control register */
 	char	res12[12];
 	uint	lbcdllcr;	/* 0xe0e20 - LBC DLL control register */
-	char	res13[256];
+	char	res13[248];
+	uint	lbiuiplldcr0;	/* 0xe0f1c -- LBIU PLL Debug Reg 0 */
+	uint	lbiuiplldcr1;	/* 0xe0f20 -- LBIU PLL Debug Reg 1 */
 	uint	ddrioovcr;	/* 0xe0f24 - DDR IO Override Control */
 	char	res14[61659];
 } ccsr_gur_t;
Index: cpu/mpc85xx/cpu.c
===================================================================
RCS file: /cm/vault/u-boot/u-boot/cpu/mpc85xx/cpu.c,v
retrieving revision 1.1.1.1.4.9
retrieving revision 1.1.1.1.4.10
diff -u -r1.1.1.1.4.9 -r1.1.1.1.4.10
--- cpu/mpc85xx/cpu.c	6 May 2005 16:58:44 -0000	1.1.1.1.4.9
+++ cpu/mpc85xx/cpu.c	18 May 2005 20:17:53 -0000	1.1.1.1.4.10
@@ -109,6 +109,13 @@
 #endif
 	clkdiv = lcrr & 0x0f;
 	if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
+#ifdef CONFIG_MPC8548
+		/*
+		 * Yes, the entire PQ38 family use the same
+		 * bit-representation for twice the clock divider values.
+		 */
+		 clkdiv *= 2;
+#endif
 		printf("LBC:%4lu MHz\n",
 		       sysinfo.freqSystemBus / 1000000 / clkdiv);
 	} else {