[U-Boot-Users] PPC 440GX ECC SDRAM configuration from U-Boot

[Chris Love]

We have U-Boot (& Linux) running on a custom board featuring a PPC
440GX.  For now we've been happy enough to get SDRAM configured and
working (no SPD eeproms), but eventually have to tackle the issue of
enabling ECC.

Per the application note from AMCC this will involve writing the entire
memory array with valid or dummy data (with ECC enabled but not
checking).  With code executing from flash, the time to iterate through
all of memory and zero it out is pretty substantial.  The complete setup
process involves changing other SDRAM configuration registers at various
steps, implying that SDRAM is getting enabled and disabled (precluding
doing this on the fly after U-Boot has relocated).

One thought here is to copy a SDRAM zeroing routine into internal SRAM
(above the initial stack and global data) and execute from there.

Has anyone else tried to tackle ECC for the 440GX, and is this a
reasonable approach to try?  Any other suggestions for someone
relatively new to the land of PPC assembly code?

Thanks in advance,

	Chris
--
Chris Love           // Continuous Computing
chris.love at ccpu.com // http://www.ccpu.com