[U-Boot-Users] Problem porting the POST instruction cache test to the MPC5200.

[Txema Lopez]

Hi all,

I'm trying to port the POST cache test to the MPC5200 and I've found 
some problems porting the cache_post_test5 function. I think the 
philosophy of the function (I think the comments are not updated) is  to 
lock an instruction in the  cache, modify the instruction position in 
memory with another instruction and verify that the instruction locked 
in the cache has been executed when we jump to the instruction . The 
locked instruction load the r3 register with a 0 value and the "new" 
instruction with a -1. When I debug the function with the gdb and the 
BDI2000 with the ddd front end I see in the Machine Code Window the 
intruction locked ( li r3, 0) but if I stepi the instruction the value 
in r3 will be -1. I can't understand what is happening. Who is telling 
the truth?.  I think the problem seems to be  with the lock proccess 
and  I have a doubt: Must I activate the intruction MMU to lock the 
cache in a MPC5200? I have read the MPC5200 core manual and this aspect 
is not clear to me. How can I see the instruction cache with the gdb (or 
BDI2000) without write a specific function ?.

Any clue will be welcomed.

Attached my test cache file for the MPC5200  based on  the cache_8xx.S file.

Thanks in advance.

Jose Maria Lopez.
 


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