[U-Boot-Users] A question about initialization of SDRAM

[蔡潋滟]

Dear all:
		I am trying to use ELDK to make a u-boot on the board with MPC852T.

		There is declaration of rtx in cpu/mpc8xx/fec.c:
*****************************************************************
		typedef volatile struct CommonBufferDescriptor {
    	cbd_t rxbd[PKTBUFSRX];		/* Rx BD */
    	cbd_t txbd[TX_BUF_CNT];		/* Tx BD */
		} RTXBD;

		static RTXBD *rtx = NULL;
******************************************************************

		And "rtx" is used in function fec_init():
******************************************************************
		if (!rtx) {
		#ifdef CFG_ALLOC_DPRAM
		rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
				 dpram_alloc_align (sizeof (RTXBD), 8));
		#else
		rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
		#endif
		}
*******************************************************************

		I think that "rtx" should be NULL at the first time fec_init() is entered,so the rtx will be given the value.
		but after the ELDK make the u-boot, "rtx" isn't NULL at the first time fec_init() is entered, it is 0xffffffff.

		Then I make some points in the u-boot source program, and finally find that:
		Before the word "memctl->memc_mbmr  = 0xD0924114" in the function initdram, rtx is NULL(0x0),but after that it
		is 0xffffffff. Part of the fuction initdram is below:
********************************************************************
long int initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	volatile iop8xx_t *iop8xxctl=&immap->im_ioport;
	long int size8, size9;
	long int Msize;
	long int size_b0 = 0;
	long int size_b1 = 0;
	
	
	memctl->memc_mptpr = 0x0800;
	memctl->memc_mstat = 0x0000;
	upmconfig (UPMB, (uint *) sdram_table, 
			sizeof (sdram_table) / sizeof (uint));
	memctl->memc_mptpr = 0x0800;


	memctl->memc_mbmr  = 0xD0924114;//---------------------------rtx is changed to 0xfffffffff from here!!!!!!!!
	Msize=0xD0924114;
	size_b0 = 0x02000000;

	
	/*
	 * The following value is used as an address (i.e. opcode) for
	 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
	 * the port size is 32bit the SDRAM does NOT "see" the lower two
	 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
	 * MICRON SDRAMs:
	 * ->    0 00 010 0 010
	 *       |  |   | |   +- Burst Length = 4
	 *       |  |   | +----- Burst Type   = Sequential
	 *       |  |   +------- CAS Latency  = 2
	 *       |  +----------- Operating Mode = Standard
	 *       +-------------- Write Burst Mode = Programmed Burst Length
	 */
	memctl->memc_mar  = 0x00000088;
	memctl->memc_mcr  = 0x8080A105;
	udelay(1);

	memctl->memc_mbmr =(Msize & 0xfffffff0) | 0x00000008;//((Msize | 0x00000008) & 0xfffffffb);
	memctl->memc_mcr =  0x8080A130;
	udelay(1);

	memctl->memc_mbmr =Msize ;
	udelay(200);
	size_b1 = 0;

*******************************************************************

I wonder what happens in "memctl->memc_mbmr  = 0xD0924114;",would you please explain it to me ? Thanks!

Liam
2005-11-17