[U-Boot-Users] MPC8347 DDR SDRAM problem!

[Ho Jeffrey-r26191]

Hi Yang,

Have you try to use the hw test to check if your DDR is setup correctly?

Before do any flash programming, check you hw.

Regards,
Jeffrey Ho 

-----Original Message-----
From: u-boot-users-admin at lists.sourceforge.net [mailto:u-boot-users-admin at lists.sourceforge.net] On Behalf Of Simon Yang
Sent: Wednesday, November 23, 2005 10:54 PM
To: U-Boot-Users at lists.sourceforge.net
Subject: [U-Boot-Users] MPC8347 DDR SDRAM problem!

Hi All,

Now I am debugging our board, CPU is MPC8347 and we use 256M DDR SDRAM(DIMM), the Flash port size is 8 bit, currently there is nothing in the Flash, we use the default Hard Code Reset Configuration Word(101), we use MetroWerks USBTAP to connect to the JTAG and we modify the 8349SYS_init_flash_uboot.cfg file, when we erase the Flash a message "Error read memory" shows in CodeWarrior, then open "Command Windows" in CodeWarrior and use "mem 10000" but "error" get, we measure the DDR CLK it is ok.
In the 8349SYS_init_flash_uboot.cfg file we modify as follow:

#setMMRBaseAddr 0xFF400000
writereg	MBAR	0xFF400000

# change internal MMR base from 0xff400000 (reset value) to 0xe0000000 writemem.l 0xff400000 0xe0000000 # IMMRBAR = 0xe0000000

#setMMRBaseAddr 0xe0000000
writereg	MBAR	0xe0000000

##############################################
# System Configuration - Local Access Windows ##############################################

# Local Bus Local Access Windows
#################################
# WINDOW 0 - configuration space - Initially mapped by RCWHR[BMS], relocated to 0xe0000000 writemem.l 0xe0000020 0xe0000000 # LBLAWBAR0  - begining at 0xe0000000

# WINDOW 1 - FLASH
writemem.l 0xe0000028 0xFE000000 # LBLAWBAR1  - begining at 0xfe000000
writemem.l 0xe000002c 0x80000016 # LBLAWAR1   - enable, size = 8MB

# DDR Local Access Windows
# WINDOW 0 - 1st DDR SODIMM
writemem.l 0xe00000a0 0x00000000 # DDRLAWBAR0 - begining at 0x00000000 writemem.l 0xe00000a4 0x8000001b # DDRLAWAR0  - enable, size = 256MB

#CS0_BNDS
writemem.l 0xe0002000 0x0000000F
#CS0_CONFIG(rows 13,columns 10)
writemem.l 0xe0002080 0x80000102

# TIMING_CONFIG_1
writemem.l 0xe0002108 0x37343321

# DDR_SDRAM_MODE
writemem.l 0xe0002118 0x20000162
# DDR_SDRAM_INTERVAL
writemem.l 0xe0002124 0x045b0100
sleep 1200
# enable the DDR memory controller
writemem.l 0xe0002110 0xc2000000

# CS0 - 8MB FLASH
writemem.l 0xe0005000 0xFE000801 # BR0 base address at 0xFE000000, port size 8 bit, GPCM, valid writemem.l 0xe0005004 0xFE006ff7 # OR0 8MB flash size, 15 w.s., timing relaxed

# LBCR - local bus enable
writemem.l 0xe00050d0 0x00000000


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