[U-Boot-Users] RE : MPC8347 DDR SDRAM problem! (Simon Yang)
Krishnan
kris at slokatelecom.com
Thu Nov 24 07:07:39 CET 2005
Hello Simon,
I had an MPC 8260 board and was using USB TAP and faced many issues with the
same while trying to load the flash with the Embedded Planet default
boot-loader. Finally I had to do the following to get the flash programmed
Problem 1: SDRAM(DDRAM) initialisation values have to be correct before you
can use Metrowerks flash programmer tool otherwise if the RAM is not
properly setup you could get many exceptions (because of refresh issues
instructions are corrupted !!).
Solution : Do you have DPRAM on MPC8347? If yes, why don't you recompile the
flash programmer application (or write one yourself - it doesn't take too
much time you see !!) and link it to the DPRAM. You don't need more than 8K
DPRAM to setup code, data, stack for this program (in fact it is less than
2K totally)
Problem 2: Many of the features in Code Warrior do not work as expected. In
fact when you put a breakpoint while debugging and if you try to dump memory
there are exceptions that are caused (some filthy interactions between the
debugger dumping memory and the PC value that the breakpoints are set on. It
seems more a bug to me than anything else !!)
Solution : Connect the USB TAP again and again and do only 1 operation at 1
time
By this procedure you can surely get the flash programmed (hope you have the
right bootloader in the default address by that way)
Let me know how it goes.
Regards,
Krishnan
>-----Original Message-----
>From: u-boot-users-admin at lists.sourceforge.net
>[mailto:u-boot-users-admin at lists.sourceforge.net]On Behalf Of
>u-boot-users-request at lists.sourceforge.net
>Sent: Thursday, November 24, 2005 9:03 AM
>To: u-boot-users at lists.sourceforge.net
>Subject: U-Boot-Users digest, Vol 1 #1625 - 13 msgs
>
>
>Send U-Boot-Users mailing list submissions to
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>
>Today's Topics:
>
> 1. MPC8347 DDR SDRAM problem! (Simon Yang)
> 2. RE: PCI_REGION_MEMORY and prefetchable PCI windows? (Rune Torgersen)
> 3. RE: PCI_REGION_MEMORY and prefetchable PCI windows? (Rune Torgersen)
> 4. RE: MPC8347 DDR SDRAM problem! (Ho Jeffrey-r26191)
> 5. [PATCH] change-tsec1-phy-addr-for-tqm8349-board.patch (Martin Krause)
> 6. RE: is there any other toolchains for u-boot of mips arch?
>(Tim Braun)
> 7. get_dcr and set_dcr in loadable apps (John Davis)
> 8. Re: MPC8347 DDR SDRAM problem! (Wolfgang Denk)
> 9. Re: RE: is there any other toolchains for u-boot of mips
>arch? (Wolfgang Denk)
> 10. [PATCH] Make System IO Config Registers board configurable
>on MPC83xx (Kumar Gala)
> 11. Re: get_dcr and set_dcr in loadable apps (Shawn Jin)
> 12. where is the interrupt vectors? (terry)
> 13. Re: where is the interrupt vectors? (KokHow Teh)
>
>--__--__--
>
>Message: 1
>Date: Wed, 23 Nov 2005 22:54:02 +0800
>From: Simon Yang <bestwish.simon at gmail.com>
>To: U-Boot-Users at lists.sourceforge.net
>Subject: [U-Boot-Users] MPC8347 DDR SDRAM problem!
>
>Hi All,
>
>Now I am debugging our board, CPU is MPC8347 and we use 256M DDR
>SDRAM(DIMM), the Flash port size is 8 bit, currently there is nothing
>in the Flash, we use the default Hard Code Reset Configuration
>Word(101), we use MetroWerks USBTAP to connect to the JTAG and we
>modify the 8349SYS_init_flash_uboot.cfg file, when we erase the Flash
>a message "Error read memory" shows in CodeWarrior, then open "Command
>Windows" in CodeWarrior and use "mem 10000" but "error" get, we
>measure the DDR CLK it is ok.
>In the 8349SYS_init_flash_uboot.cfg file we modify as follow:
>
>#setMMRBaseAddr 0xFF400000
>writereg=09MBAR=090xFF400000
>
># change internal MMR base from 0xff400000 (reset value) to 0xe0000000
>writemem.l 0xff400000 0xe0000000 # IMMRBAR =3D 0xe0000000
>
>#setMMRBaseAddr 0xe0000000
>writereg=09MBAR=090xe0000000
>
>##############################################
># System Configuration - Local Access Windows
>##############################################
>
># Local Bus Local Access Windows
>#################################
># WINDOW 0 - configuration space - Initially mapped by RCWHR[BMS],
>relocated to 0xe0000000
>writemem.l 0xe0000020 0xe0000000 # LBLAWBAR0 - begining at 0xe0000000
>
># WINDOW 1 - FLASH
>writemem.l 0xe0000028 0xFE000000 # LBLAWBAR1 - begining at 0xfe000000
>writemem.l 0xe000002c 0x80000016 # LBLAWAR1 - enable, size =3D 8MB
>
># DDR Local Access Windows
># WINDOW 0 - 1st DDR SODIMM
>writemem.l 0xe00000a0 0x00000000 # DDRLAWBAR0 - begining at 0x00000000
>writemem.l 0xe00000a4 0x8000001b # DDRLAWAR0 - enable, size =3D 256MB
>
>#CS0_BNDS
>writemem.l 0xe0002000 0x0000000F
>#CS0_CONFIG(rows 13,columns 10)
>writemem.l 0xe0002080 0x80000102
>
># TIMING_CONFIG_1
>writemem.l 0xe0002108 0x37343321
>
># DDR_SDRAM_MODE
>writemem.l 0xe0002118 0x20000162
># DDR_SDRAM_INTERVAL
>writemem.l 0xe0002124 0x045b0100
>sleep 1200
># enable the DDR memory controller
>writemem.l 0xe0002110 0xc2000000
>
># CS0 - 8MB FLASH
>writemem.l 0xe0005000 0xFE000801 # BR0 base address at 0xFE000000,
>port size 8 bit, GPCM, valid
>writemem.l 0xe0005004 0xFE006ff7 # OR0 8MB flash size, 15 w.s.,
>timing rela=
>xed
>
># LBCR - local bus enable
>writemem.l 0xe00050d0 0x00000000
>
>
>--__--__--
>
>Message: 2
>Subject: RE: [U-Boot-Users] PCI_REGION_MEMORY and prefetchable PCI windows?
>Date: Wed, 23 Nov 2005 09:05:33 -0600
>From: "Rune Torgersen" <runet at innovsys.com>
>To: "Kumar Gala" <galak at gate.crashing.org>,
> <u-boot-users at lists.sourceforge.net>
>
>> -----Original Message-----
>> From: Kumar Gala
>> Sent: Tuesday, November 22, 2005 12:51
>> Also, I'm starting to look at adding the ability to register=20
>> a PCI memory=20
>> region as prefetchable and handle allocations of devices that=20
>> have BARs=20
>> that are prefetchable. I plan on modeling this after the code that=20
>> handles pci_mem, any comments?
>
>I already have working code for U-Boot that does prefetchable
>allocation. I will send you a copy if interested.
>
>
>
>--__--__--
>
>Message: 3
>Subject: RE: [U-Boot-Users] PCI_REGION_MEMORY and prefetchable PCI windows?
>Date: Wed, 23 Nov 2005 09:06:24 -0600
>From: "Rune Torgersen" <runet at innovsys.com>
>To: "Kumar Gala" <galak at gate.crashing.org>,
> <u-boot-users at lists.sourceforge.net>
>
>=20
>
>> -----Original Message-----
>> From: Rune Torgersen=20
>> Sent: Wednesday, November 23, 2005 09:06
>> To: 'Kumar Gala'; u-boot-users at lists.sourceforge.net
>> Subject: RE: [U-Boot-Users] PCI_REGION_MEMORY and=20
>> prefetchable PCI windows?
>>=20
>> > -----Original Message-----
>> > From: Kumar Gala
>> > Sent: Tuesday, November 22, 2005 12:51
>> > Also, I'm starting to look at adding the ability to register=20
>> > a PCI memory=20
>> > region as prefetchable and handle allocations of devices that=20
>> > have BARs=20
>> > that are prefetchable. I plan on modeling this after the code that=20
>> > handles pci_mem, any comments?
>>=20
>> I already have working code for U-Boot that does prefetchable=20
>> allocation. I will send you a copy if interested.
>>=20
>
>Never mind... saw your patch, and it is almost identical to what I have
>done.=20
>
>
>--__--__--
>
>Message: 4
>From: Ho Jeffrey-r26191 <r26191 at freescale.com>
>To: Simon Yang <bestwish.simon at gmail.com>,
>U-Boot-Users at lists.sourceforge.net
>Subject: RE: [U-Boot-Users] MPC8347 DDR SDRAM problem!
>Date: Wed, 23 Nov 2005 23:12:10 +0800
>
>Hi Yang,
>
>Have you try to use the hw test to check if your DDR is setup correctly?
>
>Before do any flash programming, check you hw.
>
>Regards,
>Jeffrey Ho
>
>-----Original Message-----
>From: u-boot-users-admin at lists.sourceforge.net
>[mailto:u-boot-users-admin at lists.sourceforge.net] On Behalf Of Simon Yang
>Sent: Wednesday, November 23, 2005 10:54 PM
>To: U-Boot-Users at lists.sourceforge.net
>Subject: [U-Boot-Users] MPC8347 DDR SDRAM problem!
>
>Hi All,
>
>Now I am debugging our board, CPU is MPC8347 and we use 256M DDR
>SDRAM(DIMM), the Flash port size is 8 bit, currently there is
>nothing in the Flash, we use the default Hard Code Reset
>Configuration Word(101), we use MetroWerks USBTAP to connect to
>the JTAG and we modify the 8349SYS_init_flash_uboot.cfg file, when
>we erase the Flash a message "Error read memory" shows in
>CodeWarrior, then open "Command Windows" in CodeWarrior and use
>"mem 10000" but "error" get, we measure the DDR CLK it is ok.
>In the 8349SYS_init_flash_uboot.cfg file we modify as follow:
>
>#setMMRBaseAddr 0xFF400000
>writereg MBAR 0xFF400000
>
># change internal MMR base from 0xff400000 (reset value) to
>0xe0000000 writemem.l 0xff400000 0xe0000000 # IMMRBAR = 0xe0000000
>
>#setMMRBaseAddr 0xe0000000
>writereg MBAR 0xe0000000
>
>##############################################
># System Configuration - Local Access Windows
>##############################################
>
># Local Bus Local Access Windows
>#################################
># WINDOW 0 - configuration space - Initially mapped by RCWHR[BMS],
>relocated to 0xe0000000 writemem.l 0xe0000020 0xe0000000 #
>LBLAWBAR0 - begining at 0xe0000000
>
># WINDOW 1 - FLASH
>writemem.l 0xe0000028 0xFE000000 # LBLAWBAR1 - begining at 0xfe000000
>writemem.l 0xe000002c 0x80000016 # LBLAWAR1 - enable, size = 8MB
>
># DDR Local Access Windows
># WINDOW 0 - 1st DDR SODIMM
>writemem.l 0xe00000a0 0x00000000 # DDRLAWBAR0 - begining at
>0x00000000 writemem.l 0xe00000a4 0x8000001b # DDRLAWAR0 - enable,
>size = 256MB
>
>#CS0_BNDS
>writemem.l 0xe0002000 0x0000000F
>#CS0_CONFIG(rows 13,columns 10)
>writemem.l 0xe0002080 0x80000102
>
># TIMING_CONFIG_1
>writemem.l 0xe0002108 0x37343321
>
># DDR_SDRAM_MODE
>writemem.l 0xe0002118 0x20000162
># DDR_SDRAM_INTERVAL
>writemem.l 0xe0002124 0x045b0100
>sleep 1200
># enable the DDR memory controller
>writemem.l 0xe0002110 0xc2000000
>
># CS0 - 8MB FLASH
>writemem.l 0xe0005000 0xFE000801 # BR0 base address at 0xFE000000,
>port size 8 bit, GPCM, valid writemem.l 0xe0005004 0xFE006ff7 #
>OR0 8MB flash size, 15 w.s., timing relaxed
>
># LBCR - local bus enable
>writemem.l 0xe00050d0 0x00000000
>
>
>-------------------------------------------------------
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>
>
>--__--__--
>
>Message: 5
>Date: Wed, 23 Nov 2005 16:33:17 +0100
>From: "Martin Krause" <Martin.Krause at tqs.de>
>To: <u-boot-users at lists.sourceforge.net>
>Subject: [U-Boot-Users] [PATCH]
>change-tsec1-phy-addr-for-tqm8349-board.patch
>
>This is a multi-part message in MIME format.
>
>------_=_NextPart_001_01C5F043.3A098D2D
>Content-Type: text/plain;
> charset="iso-8859-1"
>Content-Transfer-Encoding: quoted-printable
>
>Change TSEC1_PHY_ADDR for TQM8349 board
>Patch by Martin Krause, 23 Nov 2005
>
>Change PHY address from 0 to 2 to support STK85XX.103
>
>Signed-off-by: Martin Krause <martin.krause at tqs.de>
>
>CHANGELOG:
>
>* Change TSEC1_PHY_ADDR for TQM8349 board
> Patch by Martin Krause, 23 Nov 2005
>---
>
>------_=_NextPart_001_01C5F043.3A098D2D
>Content-Type: application/octet-stream;
> name="change-tsec1-phy-addr-for-tqm8349-board.patch"
>Content-Transfer-Encoding: base64
>Content-Description: change-tsec1-phy-addr-for-tqm8349-board.patch
>Content-Disposition: attachment;
> filename="change-tsec1-phy-addr-for-tqm8349-board.patch"
>
>Q2hhbmdlIFRTRUMxX1BIWV9BRERSIGZvciBUUU04MzQ5IGJvYXJkClBhdGNoIGJ5IE1
>hcnRpbiBL
>cmF1c2UsIDIzIE5vdiAyMDA1CgpDaGFuZ2UgUEhZIGFkZHJlc3MgZnJvbSAwIHRvIDI
>gdG8gc3Vw
>cG9ydCBTVEs4NVhYLjEwMwoKLS0tCmNvbW1pdCAwZTAwYjRkZTE2ZGQ1ZTk5ZmRkZDA
>wYTczMzYw
>OTc2YzNhZDAxOTExCnRyZWUgNzM2MTAyNTI0ZWU5MjkwMzhlOTA1ZGJkMzAxZDhlZDY
>4NGEwYjdl
>OQpwYXJlbnQgNTU2OGU2MTNlZTM4ZDRiYjVkZDYwMWNkYjJmNzRlZDBkN2RlOTkwMgp
>hdXRob3Ig
>TWFydGluIEtyYXVzZSA8bWtyQHRxLXNld3Nydi00LnRxLW5ldC5kZT4gV2VkLCAyMyB
>Ob3YgMjAw
>NSAxNToxNToyMiArMDEwMApjb21taXR0ZXIgTWFydGluIEtyYXVzZSA8bWtyQHRxLXN
>ld3Nydi00
>LnRxLW5ldC5kZT4gV2VkLCAyMyBOb3YgMjAwNSAxNToxNToyMiArMDEwMAoKIGluY2x
>1ZGUvY29u
>Zmlncy9UUU04MzR4LmggfCAgICAyICstCiAxIGZpbGVzIGNoYW5nZWQsIDEgaW5zZXJ
>0aW9ucygr
>KSwgMSBkZWxldGlvbnMoLSkKCmRpZmYgLS1naXQgYS9pbmNsdWRlL2NvbmZpZ3MvVFF
>NODM0eC5o
>IGIvaW5jbHVkZS9jb25maWdzL1RRTTgzNHguaApvbGQgbW9kZSAxMDA2NDQKbmV3IG1
>vZGUgMTAw
>NzU1CmluZGV4IGMyNWE3NzcuLmJhMmY0ZWEKLS0tIGEvaW5jbHVkZS9jb25maWdzL1R
>RTTgzNHgu
>aAorKysgYi9pbmNsdWRlL2NvbmZpZ3MvVFFNODM0eC5oCkBAIC0yNDksNyArMjQ5LDc
>gQEAgZXh0
>ZXJuIGludCB0cW04MzR4X251bV9mbGFzaF9iYW5rczsKICNkZWZpbmUgQ09ORklHX01
>QQzgzWFhf
>VFNFQzFfTkFNRQkiVFNFQzAiCiAjZGVmaW5lIENPTkZJR19NUEM4M1hYX1RTRUMyCQk
>xCiAjZGVm
>aW5lIENPTkZJR19NUEM4M1hYX1RTRUMyX05BTUUJIlRTRUMxIgotI2RlZmluZSBUU0V
>DMV9QSFlf
>QUREUgkJCTAKKyNkZWZpbmUgVFNFQzFfUEhZX0FERFIJCQkyCiAjZGVmaW5lIFRTRUM
>yX1BIWV9B
>RERSCQkJMQogI2RlZmluZSBUU0VDMV9QSFlJRFgJCQkwCiAjZGVmaW5lIFRTRUMyX1B
>IWUlEWAkJ
>CTAK
>
>------_=_NextPart_001_01C5F043.3A098D2D--
>
>
>--__--__--
>
>Message: 6
>Date: Wed, 23 Nov 2005 09:47:05 -0600
>From: "Tim Braun" <tim.braun at librestream.com>
>To: <u-boot-users at lists.sourceforge.net>
>Cc: "zhuzhenhua" <zzh.hust at gmail.com>
>Subject: [U-Boot-Users] RE: is there any other toolchains for
>u-boot of mips arch?
>
>> Date: Wed, 23 Nov 2005 09:28:22 +0800
>> From: zhuzhenhua <zzh.hust at gmail.com>
>
>> to use other toolchain?
>> what need to do?
>> i change the CROSS_COMPILE in Makefile...
>
>An alternative to setting your PATH in your shell environment is to set
>a CCPATH and add that
>to the make process environment in the top-level Makefile.
>
>I'm using a uclibc built compiler under cygwin, and the compilers are
>not in my shell path:
>
>--- ..\u-boot-1.1.1-orig\Makefile 2004-04-24 18:23:30.000000000
>-0500
>+++ Makefile 2005-10-26 13:43:58.255033400 -0500
>@@ -40,7 +40,8 @@
>=20
>########################################################################
>#
>=20
> TOPDIR :=3D $(shell if [ "$$PWD" !=3D "" ]; then echo
>$$PWD; else pwd; =
>fi)
>-export TOPDIR
>+# export TOPDIR
>+# TOPDIR :=3D ../u-boot
>=20
> ifeq (include/config.mk,$(wildcard include/config.mk))
> # load ARCH, BOARD, and CPU configuration
>@@ -67,7 +68,14 @@
> endif
> endif
> ifeq ($(ARCH),mips)
>-CROSS_COMPILE =3D mips_4KC-
>+# CROSS_COMPILE =3D sde-
>+# CROSS_COMPILE =3D mips_4KC-
>+
>+# Our path to our compilers
>+CCPATH :=3D /usr/local/mipsel-linux/bin/
>+CROSS_COMPILE :=3D mipsel-linux-uclibc-
>+PATH :=3D ${PATH}:${CCPATH}
>+
> endif
> ifeq ($(ARCH),nios)
> CROSS_COMPILE =3D nios-elf-
>@@ -81,6 +89,11 @@
> endif
> endif
>=20
>+ifeq ($(HOSTOS),cygwin)
>+exeext =3D .exe
>+SHELL =3D /bin/bash
>+endif
>+
> export CROSS_COMPILE
>=20
>=20
>########################################################################
>#
>@@ -115,7 +128,7 @@
> .PHONY : $(LIBS)
>=20
> # Add GCC lib
>-PLATFORM_LIBS +=3D --no-warn-mismatch -L $(shell dirname `$(CC) =
>$(CFLAGS)
>-print-libgcc-file-name`) -lgcc
>+PLATFORM_LIBS +=3D --no-warn-mismatch -L $(shell dirname =
>`$(CCPATH)$(CC)
>$(CFLAGS) -print-libgcc-file-name`) -lgcc
>=20
>=20
> # The "tools" are needed early, so put this first
>
>Tim Braun, Sr. Des. Eng.
>LibreStream Technologies
>200-55 Rothwell Rd.
>Winnipeg R3P 2M5=20
>
>
>
>
>--__--__--
>
>Message: 7
>Date: Wed, 23 Nov 2005 11:08:33 -0500
>From: John Davis <davisjf at gmail.com>
>To: u-boot-users at lists.sourceforge.net
>Subject: [U-Boot-Users] get_dcr and set_dcr in loadable apps
>
>Hello
>
>I am trying to use get_dcr and set_dcr in my examples/app.c code. I
>added g/set_dcr to exports.h and _exports.h. but I get a lock up when
>I call them. Any idea how to access these functions from loadable
>apps?
>
>JD
>
>
>--__--__--
>
>Message: 8
>To: Simon Yang <bestwish.simon at gmail.com>
>cc: U-Boot-Users at lists.sourceforge.net
>From: Wolfgang Denk <wd at denx.de>
>Subject: Re: [U-Boot-Users] MPC8347 DDR SDRAM problem!
>Date: Wed, 23 Nov 2005 17:54:00 +0100
>
>In message <1c3e00040511230654s252a63c9t at mail.gmail.com> you wrote:
>>=20
>...
>> modify the 8349SYS_init_flash_uboot.cfg file, when we erase the Flash
>> a message "Error read memory" shows in CodeWarrior, then open "Command
>> Windows" in CodeWarrior and use "mem 10000" but "error" get, we
>...
>
>This has absolutley nothing to do with U-Boot. Please keep such
>topics off this list. Thanks.
>
>
>Wolfgang Denk
>
>--=20
>Software Engineering: Embedded and Realtime Systems, Embedded Linux
>Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
>Horses just naturally have mohawk haircuts.
>
>
>--__--__--
>
>Message: 9
>To: "Tim Braun" <tim.braun at librestream.com>
>cc: u-boot-users at lists.sourceforge.net,
> "zhuzhenhua" <zzh.hust at gmail.com>
>From: Wolfgang Denk <wd at denx.de>
>Subject: Re: [U-Boot-Users] RE: is there any other toolchains for
>u-boot of mips arch?
>Date: Wed, 23 Nov 2005 17:57:42 +0100
>
>In message <8230E1CC35AF9F43839F3049E930169A1F5EDB at yang.LibreStream.local=
>> you wrote:
>>
>> > i change the CROSS_COMPILE in Makefile...
>>=20
>> An alternative to setting your PATH in your shell environment is to set
>> a CCPATH and add that
>> to the make process environment in the top-level Makefile.
>
>Folks, please *stop* messing with the Makefile. This is *N*O*T*
>necessray. All you need to do is to set the CROSS_COMPILE variable in
>your environment (and make sure the required directories are in your
>PATH).
>
>Best regards,
>
>Wolfgang Denk
>
>--=20
>Software Engineering: Embedded and Realtime Systems, Embedded Linux
>Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
>What the gods would destroy they first submit to an IEEE standards
>committee.
>
>
>--__--__--
>
>Message: 10
>Date: Wed, 23 Nov 2005 14:31:32 -0600 (CST)
>From: Kumar Gala <galak at gate.crashing.org>
>To: u-boot-users at lists.sourceforge.net
>cc: Wolfgang Denk <wd at denx.de>
>Subject: [U-Boot-Users] [PATCH] Make System IO Config Registers
>board configurable on MPC83xx
>
>Make System IO Config Registers board configurable on MPC83xx
>
>Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
>
>CHANGELOG:
>* Make System IO Config Registers board configurable on MPC83xx
> Patch by Kumar Gala 23 Nov 2005
>
>---
>commit 01b445b70c5e296c115b93a894ff3c7ffc1586d5
>tree 2a2398b1bd34aa9b79e7ba34b4ccf7c28c932734
>parent f6a259d086597f691d821a5ac2181ce249fad987
>author Kumar Gala <galak at kernel.crashing.org> Wed, 23 Nov 2005
>14:31:37 -0600
>committer Kumar Gala <galak at kernel.crashing.org> Wed, 23 Nov 2005
>14:31:37 -0600
>
> cpu/mpc83xx/cpu_init.c | 8 ++++++--
> include/configs/MPC8349ADS.h | 4 ++++
> include/configs/TQM834x.h | 4 ++++
> 3 files changed, 14 insertions(+), 2 deletions(-)
>
>diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
>index dcb3445..e75b8b7 100644
>--- a/cpu/mpc83xx/cpu_init.c
>+++ b/cpu/mpc83xx/cpu_init.c
>@@ -63,8 +63,12 @@ void cpu_init_f (volatile immap_t * im)
> im->sysconf.spcr |= SPCR_TBEN;
>
> /* System General Purpose Register */
>- im->sysconf.sicrh = SICRH_TSOBI1;
>- im->sysconf.sicrl = SICRL_LDP_A;
>+#ifdef CFG_SICRH
>+ im->sysconf.sicrh = CFG_SICRH;
>+#endif
>+#ifdef CFG_SICRL
>+ im->sysconf.sicrl = CFG_SICRL;
>+#endif
>
> /*
> * Memory Controller:
>diff --git a/include/configs/MPC8349ADS.h b/include/configs/MPC8349ADS.h
>index 41309ac..7197e0f 100644
>--- a/include/configs/MPC8349ADS.h
>+++ b/include/configs/MPC8349ADS.h
>@@ -504,6 +504,10 @@
> HRCWH_TSEC2M_IN_GMII )
> #endif
>
>+/* System IO Config */
>+#define CFG_SICRH SICRH_TSOBI1
>+#define CFG_SICRL SICRL_LDP_A
>+
> #define CFG_HID0_INIT 0x000000000
>
> #define CFG_HID0_FINAL CFG_HID0_INIT
>diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
>index c25a777..a2184ee 100644
>--- a/include/configs/TQM834x.h
>+++ b/include/configs/TQM834x.h
>@@ -417,6 +417,10 @@ extern int tqm834x_num_flash_banks;
> HRCWH_TSEC2M_IN_GMII )
> #endif
>
>+/* System IO Config */
>+#define CFG_SICRH SICRH_TSOBI1
>+#define CFG_SICRL SICRL_LDP_A
>+
> /* i-cache and d-cache disabled */
> #define CFG_HID0_INIT 0x000000000
> #define CFG_HID0_FINAL CFG_HID0_INIT
>
>
>
>--__--__--
>
>Message: 11
>Date: Wed, 23 Nov 2005 14:32:02 -0800
>From: Shawn Jin <shawnxjin at gmail.com>
>To: John Davis <davisjf at gmail.com>
>Subject: Re: [U-Boot-Users] get_dcr and set_dcr in loadable apps
>Cc: u-boot-users at lists.sourceforge.net
>
>> I am trying to use get_dcr and set_dcr in my examples/app.c code. I
>> added g/set_dcr to exports.h and _exports.h. but I get a lock up when
>> I call them. Any idea how to access these functions from loadable
>> apps?
>
>You also need to add to-be-exported functions to the jump table in
>exports.=
>c
>
>-Shawn.
>
>
>--__--__--
>
>Message: 12
>From: terry <tqiu at neuros.com.cn>
>Reply-To: tqiu at neuros.com.cn
>To: u-boot-users at lists.sourceforge.net
>Date: Thu, 24 Nov 2005 11:08:17 +0800
>Subject: [U-Boot-Users] where is the interrupt vectors?
>
>hello,
>
>I am new to u-boot.
>I want to support some perpherals which need use the I/O pins of INT.
>And it need to be allocated the vectors, depending on the INT ports.
>How does u-boot support this, and where I can find it?
>
>Thank you,
>
>Terry
>
>
>
>
>
>--__--__--
>
>Message: 13
>Subject: Re: [U-Boot-Users] where is the interrupt vectors?
>To: u-boot-users at lists.sourceforge.net
>From: "KokHow Teh" <KokHow.Teh at marconi.com>
>Date: Thu, 24 Nov 2005 11:32:24 +0800
>
>
>
>
>>I want to support some perpherals which need use the I/O pins of INT.
>>And it need to be allocated the vectors, depending on the INT ports.
>>How does u-boot support this, and where I can find it?
>
>Depending on your CPU architecture, interrupt/exception vectors are setup
>in start.S
>
>
>
>
>
>
>
>--__--__--
>
>_______________________________________________
>U-Boot-Users mailing list
>U-Boot-Users at lists.sourceforge.net
>https://lists.sourceforge.net/lists/listinfo/u-boot-users
>
>
>End of U-Boot-Users Digest
>
>
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