[U-Boot-Users] Re: Can't get correct VSC8201 PHYID on MPC8347 in uboot-1.1.3 issue

[Simon Yang]

Hi David,

I have checked the config file settings, they are correct.

For the MDIO I get nothing on MDIO read frame and write frame of SMI
when the uboot is running.What's wrong with it?



2005/11/29, David Updegraff <dave at cray.com>:
> Simon
>
> check your config file settings for:
>
> #define TSEC1_PHY_ADDR          0
> #define TSEC1_PHYIDX            0
> #define TSEC2_PHY_ADDR          1
> #define TSEC2_PHYIDX            0
>
> for sanity of MDIO stuff.
>
> > Dear All,
> >
> > Now I use VSC8201PHY on MPC8347 with uboot-1.1.3,I think VSC8201 PHY
> > is similar to CIS8201PHY,so I add struct phy_info_vsc8201 based on
> > struct phy_info_cis8201 in tsec.c and related registers in tsec.h, but
> > during bootup I meet below problem in tsec.c when it goes to read
> > phy_id in function read_phy_reg(), the phy_id is always ffffffff, the
> > log file is as follow:
> >
> > Net:   TSEC initialize begin...
> > In Read reg func PHY ID is:0
> > Register number MIIMADD is 2
> > PHY Reg after read PHYIR1 is:ffff
> > PHY Reg High 16 bit is:ffff0000
> > Begin Read phy reg!
> > In Read reg func PHY ID is:0
> > Register number MIIMADD is 3
> > PHY Reg after read PHYIR2 is:ffff
> > Tsec: read from reg is ffffffff
> > Freescale TSEC0: PHY id ffffffff is not supported!
> > Freescale TSEC0: No PHY found
> > TSEC initialize begin...
> > In Read reg func PHY ID is:1
> > Register number MIIMADD is 102
> > PHY Reg after read PHYIR1 is:ffff
> > PHY Reg High 16 bit is:ffff0000
> > Begin Read phy reg!
> > In Read reg func PHY ID is:1
> > Register number MIIMADD is 103
> > PHY Reg after read PHYIR2 is:ffff
> > Tsec: read from reg is ffffffff
> > Freescale TSEC1: PHY id ffffffff is not supported!
> > Freescale TSEC1: No PHY found
> > Freescale TSEC0, Freescale TSEC1
> >
> > Thanks in advance.
> >
> > Best Regards
> > SImon
> >
> >
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