[U-Boot-Users] MPC83xx SPI driver

Ben Warren bwarren at qstreams.com
Fri Dec 8 00:31:42 CET 2006

On Thu, 2006-12-07 at 23:49 +0100, Joakim Tjernlund wrote:

> Didn't find any other SPI driver. Looked at the docs
> for SPI in CPU mode for 832x and I don't get the command register
> where one is supposed to set a bit if the char one is about to TX is 
> the last one in a frame. Should I just set that bit at driver
> init and be done with it?
>  Jocke

Maybe somebody from Freescale can weigh in on this one.  The 83xx driver
that's in the Linux kernel doesn't touch this bit (LTS).  The 834x
manual says that if LTS is set before the last character is written, an
LT event will occur after physical transmission is complete.  In my
experience LT never fires regardless of LTS state.  With the 834x the
LTS scheme seems a bit pointless since there's only one transmit buffer.
I'm guessing the LTS isn't really implemented and the documentation was
cut'n'pasted from another chip.  

On CPM-based chips like yours, it might be useful to queue a bunch of
buffers, start them off and then be interrupted when transmission's
complete, just as you would with Ethernet, HDLC or whatever.  I guess it
depends how big your messages are.  If they're short and fit in a single
buffer, you could probably just ignore LTS, mask off the LT interrupt
and move on.


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