[U-Boot-Users] MPC8360E & Large DDR Capacities

Russell McGuire rmcguire at videopresence.com
Tue Dec 19 00:58:32 CET 2006


I found the first error.

The MPC8360EMDS.c file is missing a single write during the startup
sequence. This is also an error in the MPC8360E family manual I found about
2 weeks ago, though I notified Freescale, nobody has issued a revised manual

The DDR_SDRAM_CLK_CNTL register is missing two bit fields in the manual,
though it's the same as the MPC8349E so one can read the 8349E manual to get
the right info, see in the MPC8360E for the bad info.

Anyway added the following line to the MPC8360EMDS board and now DDR will


im->ddr.sdram_clk_cntl = 0x83000000;

Note the '8' is the undocumented bit. SS_EN I think is the name.

Anyway, now I can get up to the 'relocate_code' call. So we'll see if the
DDR is stable enough for full speed execution.

Russell McGuire
Systems Engineer
VideoPresence, Inc.
rmcguire at videopresence.com

-----Original Message-----
From: Timur Tabi [mailto:timur at freescale.com] 
Sent: Monday, December 18, 2006 3:32 PM
To: rmcguire at videopresence.com
Cc: u-boot-users at lists.sourceforge.net
Subject: Re: [U-Boot-Users] MPC8360E & Large DDR Capacities

Russell McGuire wrote:

> I think the DDR init is failing due to the udelay(200) function early in
> MPC8360E-MDS board files. The delay does not seem to be operational, so I
> 'think' the DDR gets enabled before the specked 200us delay that the
> manual requires.

Have you tried creating your own delay function that waits several seconds,
to be sure?  A for-loop would do.

Timur Tabi
Linux Kernel Developer @ Freescale

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