[U-Boot-Users] RE: changing core frequency in omap 5912

[Hunter, Jon]

Hi Sriram, HK,


> -----Original Message-----
> From: linux-omap-open-source-bounces at linux.omap.com
[mailto:linux-omap-
> open-source-bounces at linux.omap.com] On Behalf Of Hiroki Kaminaga
> Sent: Monday, February 13, 2006 2:19 AM
> To: vshrirama at gmail.com
> Cc: u-boot-users at lists.sourceforge.net; linux-omap-open-
> source at linux.omap.com
> Subject: Re: changing core frequency in omap 5912
> 
> Hi,
> 
> >     How do i change the cpu core frequency in omap 5912.
> >
> >     I tried changing the DPLL registers. but u-boot hangs.
> 
> writing clock control value(0x050f) to address(0xfffece00)?
> 
> 

You need to take care when modifying the DPLL1 and the ARM_CKCTL
register. Simply configuring the DPLL1 for 192MHz will not work, as by
default uboot configures the device for what is know as "fully scalable
mode", where the ARM, DSP and Traffic Controller (TC) run at the DPLL1
speed. The TC can NOT operate at 192MHz. It is limited to 96MHz.
Therefore, before configuring the DPLL1 and ARM_CKCTL, you need to put
the device into "synchronous scalable" mode where the ARM, DSP and TC
can run at different speeds determined by the ARM_CKCTL register. 

So here is what you need to do:

1). Make sure the DPLL1 is in bypass
2). Configure the ARM_SYSST for "synchronous scalable" mode
3). Configure the ARM_CKCTL register so that the different clock domains
operate no faster than the maximum speed for that particular domain. See
"OMAP5912 Global Clock Rules" in the OMAP5912 Errata guide for a list
showing the maximum speed for each clock domain
(http://focus.ti.com/docs/prod/folders/print/omap5912.html)
4). Configure DPLL1. 

Regards,
Jon