[U-Boot-Users] MC9328MXL/1 SDRAM initialization

[Paolo Broggini]

llandre ha scritto:
> I have a question about how MC9328MXL/1 initializes SDRAM memories.
> These is the instructions used to set up the Mode Command Register (file 
> board/mx1ads/lowlevel_init.S) for MX1ADS evalutaion board:
> 
> /* Issue Mode Register Command        */
>     ldr  r3, =0x08111800     /* Mode Register Value         */
>     ldr  r2, [r3]
> 

> Thus, when writing to address 0x08111800, microprocessor address lines 
> from A8 to A6 are set to 0. It implies that SDRAM address lines from A6 
> to A4 are set to 0. These lines are decoded by the SDRAM chips as CAS 
> latency. Allowed values are 010 (CAS latency = 2) and 011 (CAS latency = 
> 3). The value 000 is reserved.
No,

  So I think I'm misunderstanding how the
> SDRAM controller works. 
Yes, it is the way SDRAM controller "translates" the linear address in raw and col.
See the Freescale's application note AN2478

Best regards,
-Paolo