[U-Boot-Users] [PATCH] logic error waiting for init in virtex2/spartan2/spartan3

[Andrew Dyer]

In the xilinx download code there is a logic error in the section
where it is waiting for the init signal to go inactive.

There is a while loop which loop if init is active /or/ busy is
active, instead it checks if init is active /and/ busy active.  In
most designs busy is never used (only needed for clocks > 50 MHz) and
often not connected.  If the unused busy function returns 0 (not busy)
the while loop will exit early and configuration will start too soon.
This behaviour is masked if the debugging code is turned on by the
printf run time.

CHANGELOG

fix init wait loop exit conditions for xilinx downloads to properly
handle case where busy is low
Patch by Andrew Dyer <amdyer at gmail.com>, 18 July 2006

Signed-off-by: Andrew Dyer <amdyer at gmail.com>


-- 
Hardware, n.:
        The parts of a computer system that can be kicked.
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