[U-Boot-Users] [DNX#2006072742000044] [PATCH] fix the incorrect dcbz operation of 83xx

[DENX Support System]

Hello list,

inside the automatic U-Boot patch tracking system a new ticket
[DNX#2006072742000044] was created:

<snip>
> All,
> 
> The 834x Rev1.1 silicon has one bug inside. The issue is when the dcache
> locked with HID0[DLOCK], the dcbz instruction looks like no-op
> instruction.
> 
> The right behavior of the dcache is when the dcache locked with
> HID0[DLOCK], the dcbz instruction allocates new tags in cache.
> 
> The bug is only in 834x rev1.1, PVR is 0x80830011. The 834x rev2.0 and
> later and 8360 have not this bug inside. 
> 
> So, when 834x rev2.0/8360 are working with ECC, the dcbz instruction
> will corrupt the stack in cache, the processor will checkstop reset.
> 
> However, the 834x rev1.1 can work with ECC with these code, because the
> sillicon has this cache bug. The dcbz will not corrupt the stack in
> cache. Really, it is the fault code running fault sillicon.
> 
> This patch fix the incorrect dcbz operation. Instead of CPU FP writing
> to initialise the ECC.
> 
> 
> CHANGELOG:
> * fix the incorrect dcbz operation instead of CPU FP writing to
> initialise
>   the ECC memory.
>   Patch by Dave Liu, 21 July 2006
> 
> 
> 
> diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index
> 48624fe..8eaa6f6 100644
> --- a/cpu/mpc83xx/spd_sdram.c
> +++ b/cpu/mpc83xx/spd_sdram.c
> @@ -429,54 +429,37 @@ static __inline__ unsigned long get_tbms
>  /* #define CONFIG_DDR_ECC_INIT_VIA_DMA */
>  void ddr_enable_ecc(unsigned int dram_size)
>  {
> -       uint *p;
>         volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
>         volatile ddr8349_t *ddr = &immap->ddr;
>         unsigned long t_start, t_end;
> +       register u64 *p;
> +       register uint size;
> +       unsigned int pattern[2];
>  #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
>         uint i;
>  #endif
> -
> -       debug("Initialize a Cachline in DRAM\n");
>         icache_enable();
> +       t_start = get_tbms();
> 
> -#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
> -       /* Initialise DMA for direct Transfers */
> -       dma_init();
> -#endif
> -
> -       t_start = get_tbms();
> +       pattern[0] = 0xdeadbeef;
> +       pattern[1] = 0xdeadbeef;
> 
>  #if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
> -       debug("DDR init: Cache flush method\n");
> -       for (p = 0; p < (uint *)(dram_size); p++) {
> -               if (((unsigned int)p & 0x1f) == 0) {
> -                       ppcDcbz((unsigned long) p);
> -               }
> -
> -               /* write pattern to cache and flush */
> -               *p = (unsigned int)0xdeadbeef;
> -
> -               if (((unsigned int)p & 0x1c) == 0x1c) {
> -                       ppcDcbf((unsigned long) p);
> -               }
> +       debug("DDR init: CPU FP write method\n");
> +       size = dram_size;
> +       for (p = 0; p < (u64*)(size); p++) {
> +               ppcDWstore((u32*)p, pattern);
>         }
> +       __asm__ __volatile__("sync");
>  #else
> -       printf("DDR init: DMA method\n");
> -       for (p = 0; p < (uint *)(8 * 1024); p++) {
> -               /* zero one data cache line */
> -               if (((unsigned int)p & 0x1f) == 0) {
> -                       ppcDcbz((unsigned long)p);
> -               }
> -
> -               /* write pattern to it and flush */
> -               *p = (unsigned int)0xdeadbeef;
> -
> -               if (((unsigned int)p & 0x1c) == 0x1c) {
> -                       ppcDcbf((unsigned long)p);
> -               }
> +       debug("DDR init: DMA method\n");
> +       size = 0x2000;
> +       for (p = 0; p < (u64*)(size); p++) {
> +               ppcDWstore((u32*)p, pattern);
</snip>

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