[DNX#2006033142000703] [U-Boot-Users] [PATCH] Update board NetStar

[DENX Support System]

Hello list,

inside the automatic U-Boot patch tracking system a new ticket
[DNX#2006033142000703] was created:

<snip>
> Just to sync my local tree with public one. Generated against
> testing-NAND branch.
> 
> Signed-off-by: Ladislav Michl <ladis at linux-mips.org>
> 
> CHANGELOG:
> * Update board NetStar
>   Patch by Ladislav Michl, 3 Nov 2005
>   
> 
> diff --git a/board/netstar/crcek.S b/board/netstar/crcek.S
> --- a/board/netstar/crcek.S
> +++ b/board/netstar/crcek.S
> @@ -13,6 +13,7 @@
>   *	u32 - crc32
>   */
>  
> +#include <config.h>
>  #include "crcek.h"
>  
>  /**
> @@ -39,7 +40,7 @@
>  	.macro crcuj, offset, size
>  	mov	r0, #0
>  	ldr	r1, \offset
> -	ldr	r2, [r1]
> +	ldr	r2, [r1], #4
>  	cmp	r2, r0		@ no data, no problem
>  	beq	2f
>  	tst	r2, #3		@ unaligned size
> @@ -47,7 +48,6 @@
>  	ldr	r3, \size
>  	cmp	r2, r3		@ bogus size
>  	bhi	2f
> -	add	r1, r1, #4
>  	do_crc32
>  	ldr	r1, [r1]
>  2:
> @@ -55,16 +55,71 @@
>  	.endm
>  
>  	.macro wait, reg
> -	mov	\reg, #0x1000
> +	mov	\reg, #0x100000
>  3:
>  	subs	\reg, \reg, #0x1
>  	bne 	3b
> -
>  	.endm
> +
>  .text
>  .globl crcek
>  crcek:
> -	b	crc2_bad
> +	/* Enable I-cache */
> +	mrc	p15, 0, r1, c0, c0, 0		@ read C15 ID register
> +	mrc	p15, 0, r1, c0, c0, 1		@ read C15 Cache information register
> +	mrc	p15, 0, r1, c1, c0, 0		@ read C15 Control register
> +	orr	r1, r1, #0x1000			@ enable I-cache, map interrupt vector
> 0xffff0000
> +	mcr	p15, 0, r1, c1, c0, 0		@ write C15 Control register
> +	mov	r1, #0x00
> +	mcr	p15, 0, r1, c7, c5, 0		@ Flush I-cache
> +	nop
> +	nop
> +	nop
> +	nop
> +
> +	/* Setup clocking mode */
> +	ldr	r0, MPU_CLKM_BASE		@ base of CLOCK unit
> +	ldrh	r1, [r0, #0x18]			@ ARM_SYST - get reset status
> +	bic	r1, r1, #(7 << 11)		@ clear clock select
> +	orr	r1, r1, #(2 << 11)		@ set synchronous scalable
> +	mov	r2, #0
> +loop:
> +	cmp	r2, #1				@ this loop will wait for at least 100 cycles
> +	streqh	r1, [r0, #0x18]			@ before issuing next request from MPU
> +	add	r2, r2, #1			@ on the 1st run code is loaded into I-cache
> +	cmp	r2, #16				@ and second run will set clocking mode
> +	bne	loop
> +	nop
> +
> +	/* Setup clock dividers */
> +	ldr	r1, CKCTL_VAL
> +	orr	r1, r1, #0x2000			@ enable DSP clock
> +	strh	r1, [r0]			@ setup clock divisors
> +
> +	/* Setup DPLL to generate requested freq */
> +	ldr	r0, DPLL1_BASE			@ base of DPLL1 register
> +	mov	r1, #0x0010			@ set PLL_ENABLE
> +	orr	r1, r1, #0x2000			@ set IOB to new locking
> +	orr	r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
> +	orr	r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
> +	strh	r1, [r0]			@ write
> +
> +locking:
> +	ldrh	r1, [r0]			@ get DPLL value
> +	tst	r1, #0x01
> +	beq	locking				@ while LOCK not set
> +
</snip>

Your U-Boot support team