[U-Boot-Users] u-boot, 8548 and gdb

[Charles J Gillan]

I am trying to debug U-Boot on an 8548 based board. 

The tool chain is from ELDK 4.0 and I am using a BDI2000.

Up to now have used the TI instruction to step through the
assembler line by line with the BDI2000. I am now at 

             board_init_f

and want to start using gdb to speed things up.

However when rebooting the board and connecting gdb I get an unexpected
result. The code is not at 0xfffffffc as expected:

   [root at d6157 u-boot-27-apr-2006]# ppc_85xx-gdb u-boot

   GNU gdb Red Hat Linux (6.3.0.0-1.21_1rh)
   Copyright 2004 Free Software Foundation, Inc.
   GDB is free software, covered by the GNU General Public License, 

   This GDB was configured as "--host=i386-redhat-linux 
                               --target=ppc-linux"...

   (gdb) target remote xxx.xxx.xxx.xxx:2001

   Remote debugging using xxx.xxx.xxx.xxx:2001

   0xd8f61fc2 in ?? ()

   (gdb)

while the terminal window connected to the BDI2000 has the following:

   ipax8548E_ubt>info
      Target CPU        : MPC8548 Rev.1
      Target state      : halted
      Debug entry cause : unknown
      Current PC        : 0xfffffffc
      Current CR        : 0x00000000
      Current MSR       : 0x00000000
      Current LR        : 0x00000000
      Current CCSRBAR   : 0x0_ff700000
   ipax8548E_ubt>

The BDI config file contains the following:

[INIT]
WM32    0xFF7E0F08  0x00000008  ;Clear bit 30 in the engineering only
register
                                ;(CCSR space register at offset 0xe0f08)
WSPR   1009  0x00001000   ; Enable ABE bit see Errata for 8548E Rev 1

WSPR  63  0xffff0000 ; IVPR to boot core 
WSPR  415 0x0000f000 ; IVOR15 - debug exception

[TARGET]
CPUTYPE     8548        ;the CPU type
JTAGCLOCK   2           ;use 4 MHz JTAG clock - needed for Flash.
STARTUP     HALT        ;halt core while HRESET is asserted
BREAKMODE   HARD      	;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODE    HWBP        ;JTAG or HWBP, HWBP uses a hardware breakpoint
WAKEUP      500         ;give reset time to complete
POWERUP     5000        ;start delay after power-up detected in ms

Is there anything obvious that is wrong here ?

Thanks,

Charles.

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Dr Charles J Gillan
The Institute of Electronics, Communications and 
       Information Technology (ECIT),               
Queen's University Belfast, Titanic Quarter
Queen’s Road, Queen’s Island,  Belfast, BT3 9DT
Northern Ireland, UK
 
Tel:  +44 (0) 2890 971847
Fax: +44 (0) 2890 971702
  
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