[U-Boot-Users] u-boot fails at cpu_init_f

[Charles J Gillan]

Gordon,

   The piece of code which you mention:

       fff82e5c:	80 01 00 14 	lwz     r0,20(r1)
       fff82e60:	38 21 00 10 	addi    r1,r1,16

   is part of the "return" process from the routine back 
   to its caller. r1 is pointing at the C run-time stack.

   The code that sets up this stack is in the assembler routine

         in_flash  

   in file start.S for the 85xx cpus.

   Usually, the 8540 is configured so that the initial runtime 
   stack consists of 16 KB of memory locked into L1 cache meaning
   that the L1 cache is in effect providing the actual RAM.

   You might need to check the configuration in init.S for your
   board to see that this is being set up properly and then check that
   the address range is configured into TLB0 during execution.

Charles. 




-----Original Message-----
From: u-boot-users-admin at lists.sourceforge.net
[mailto:u-boot-users-admin at lists.sourceforge.net] On Behalf Of shangway
Sent: 09 May 2006 03:58
To: u-boot-users at lists.sourceforge.net
Subject: [U-Boot-Users] u-boot fails at cpu_init_f

Hi all,

I'm trying to get u-boot to run on a proprietary 8540
based board. The board is similar to the MPC8540ADS
which configuration I used to build u-boot. I am using
eldk 4.0. I managed to download u-boot to flash, but I
am unable to run it. By stepping through the code, I
found that it fails in the first c-function
"cpu_init_f". 

This is the assembly code for cpu_init_f:

fff82e10 <cpu_init_f>:
fff82e10:	94 21 ff f0 	stwu    r1,-16(r1)
fff82e14:	3c 60 e4 01 	lis     r3,-7167
fff82e18:	7c 08 02 a6 	mflr    r0
fff82e1c:	60 63 3f 80 	ori     r3,r3,16256
fff82e20:	38 80 00 00 	li      r4,0
fff82e24:	38 a0 00 30 	li      r5,48
fff82e28:	90 01 00 14 	stw     r0,20(r1)
fff82e2c:	48 00 59 b1 	bl      fff887dc <memset>
fff82e30:	3c 00 ff 00 	lis     r0,-256
fff82e34:	3d 20 e0 00 	lis     r9,-8192
fff82e38:	60 00 18 01 	ori     r0,r0,6145
fff82e3c:	3d 60 ff 00 	lis     r11,-256
fff82e40:	90 09 50 00 	stw     r0,20480(r9)
fff82e44:	61 6b 6f f7 	ori     r11,r11,28663
fff82e48:	38 00 e1 f1 	li      r0,-7695
fff82e4c:	91 69 50 04 	stw     r11,20484(r9)
fff82e50:	3d 40 f8 00 	lis     r10,-2048
fff82e54:	90 09 50 24 	stw     r0,20516(r9)
fff82e58:	61 4a 08 01 	ori     r10,r10,2049
fff82e5c:	80 01 00 14 	lwz     r0,20(r1)
fff82e60:	38 21 00 10 	addi    r1,r1,16
fff82e64:	91 49 50 20 	stw     r10,20512(r9)
fff82e68:	7c 08 03 a6 	mtlr    r0
fff82e6c:	4e 80 00 20 	blr
fff82e70:	00 02 86 0c 	.long 0x2860c

The code runs fine (at least that's what I think)
until  0xfff82e5c. The cpu hangs when I try to execute
that instruction. This is the first time, that there
is a load from an address which is not in flash, so I
suspect, that setting up the cache as RAM failed. 
I also tried to manually write data to that location
with gdb, but I read only 0x0.
As this is still in the initialization process of the
cpu, I don't think that it is related to a possibly
wrong board configuration, or am I wrong.

Any ideas?

Thanks in advance and best regards,

Gordon.

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