[U-Boot-Users] Re: SCMR[PLLMF] and HRCW for MPC8272

[Dmytro Bablinyuk]

> 
>> I am trying to bring up a custom 8272 board.
>> I set HRCW to 0x0A74B20A and on output I have
>>
>> --8<---
>> MPC8272 Clock Configuration
>>   - Bus-to-Core Mult 4x, VCO Div 2, 60x Bus Freq  25-75 , Core Freq
>> 100-300
>>   - dfbrg 1, corecnf 0x1a, busdf 5, cpmdf 1, plldf 0, pllmf 2
>>   - vco_out  198000000, scc_clk   49500000, brg_clk   12375000
>>   - cpu_clk  264000000, cpm_clk   99000000, bus_clk   66000000
>>   - pci_clk   33000000
>>
>> CPU:   MPC8272 (HiP7 Rev 14, Mask 1.0 1K50M) at 264 MHz
>> <HANGS HERE..>
>> --8<---
>>
>> BUS_CLK=66MHz - Correct.
>> CPU_CLK=264MHz - Correct
>> BUSDF=5 - Wrong! Should be BUSDF=3
>> PLLMF=2 - Wrong! Should be PLLMF=3
>> CPM_CLK=99MHz - Wrong! Should be 132MHz
>> ( PLLMF = 2(CPM_CLK/CLKIN)-1 => which gives us CPM_CLK = 99MHz )
>>
>> The problem is that PLLMF should be 3 that will give us CPM_CLK=132MHz.
>>
>> I am using MODCK_H=1010 and PCI_MODCK=0 which according to clock 
>> configuration for PCI host mode should give CPM multiplication factor 
>> equals 2 and PLLMF=3. But PLLMF still gives me 2!
>>
>> Can anybody help me please, what I am missing? How do I get PLLMF=3 in
>> SCMR?
>>
> In the Clock Configurations for PCI Host Mode and PCI_MODCK=0 in the
> Hadrware Specifications doc. from Freescale I couldn't find any options for
> MODCK_H=1010 and bus_CLK of 66MHz. Check this, maybe the problem
> is about that.
> 
> Couls you also check the MODCK[1-3] hardware pins and report?

Thank you Alex,

You were right, my mistake. MODCK[1-3] hardware pins are '000' and for 
BUS_CLK of 66MHz I have chosen MODCK_H=0000 and it works now!

Thank you very much again,

Dimitry