[U-Boot-Users] [PATCH] MPC83xx platform memory access perform ance improved

[Liu Dave-r63238]

> > > 2. Memory write
> > > When ECC enable, CPU write with 64bit. It makes DDR bus more
> > > effective.
> > 
> > we need to be careful with this since not all 83xx have the ability
> > to do 64bit writes (832x doesn't have FP)
> 
> Also, what will happen on a 32 bit wide bus? [This was  the  
> szenario in our case - a 32 bit wide memory interface.]
> 

32 bit wide DDR bus, the burst len is 8.

1. if 32 bit write on a 32 bit wide DDR bus

When cpu write with 32 bit to memory, 
The CSB bus transaction will be single beat with 4 bytes size,
The DDR bus transaction will be eight-burst with 4 bytes available,
The other bytes will be masked with DM[x]. Basically 1/8 avaliable
on one transaction 


2. if 64 bit write on a 32 bit wide DDR bus

When cpu write with 64 bit to memory,
The CSB bus transaction will be single beat with 8 bytes size,
The DDR bus transaction will be eight-burst with 8 bytes available,
The other bytes will be masked with DM[x]. Basically 1/4 avaliable
on one transaction.

I think the 64 bit write performance will double than 32 bit write on a 32 bit DDR bus.

Dave