[U-Boot-Users] Please pull u-boot-83xx.git (I2C rework)

[Joakim Tjernlund]

> -----Original Message-----
> From: Ben Warren [mailto:bwarren at qstreams.com] 
> Sent: den 28 november 2006 19:18
> To: Timur Tabi
> Cc: Joakim Tjernlund; Stefan Roese; 
> u-boot-users at lists.sourceforge.net; Kim Phillips; Wolfgang Denk
> Subject: Re: [U-Boot-Users] Please pull u-boot-83xx.git (I2C rework)
> 
> On Tue, 2006-11-28 at 12:04 -0600, Timur Tabi wrote:
> > Joakim Tjernlund wrote:
> > 
> > > I think that the I2C_READ and I2C_WRITE #defines in 
> fsl_i2c.h conflicts
> > > with
> > > soft I2C.
> > 
> > Can you be more specific?  These two macros are defined in 
> a variety of ways in 
> > U-Boot.  Soft I2C is not used on any Freescale parts (AFAIK).
> > 
> While it's not used on any Freescale evaluation boards, it could
> certainly be implemented on boards with Freescale CPUs.  I'm not sure
> why you'd bit-bang I2C if you have nice hardware controllers, 
> but there
> may be situations where this makes sense.  On the other hand, I don't
> know if SOFT_I2C and HARD_I2C can co-exist.

I use it in u-boot to send an I2C reset sequence* 
which the hardware controller can't do(or so Freescale tells me).
Futhermore, one can not use the I2C pins as GPIO on
these parts, so I had to connect two pins from PORT D** to
the I2C bus to do the bitbanging. If someone knows if this
can be done differently, I am all ears.

so I removed I2C_READ/I2C_WRITE from asm-ppc/i2c.h
and renamed I2C_READ to I2C_READ_BIT(same for write)
locally in cpu/mpc83xx/i2c.c(now renamed to fsl-i2c.c)

* The reset sequence in soft i2c isn't complete. One has
  to send a start in each clock cycle as well.

** Something isn't working properly with PORTD in ODR mode.
   I have change direction from output to input for SDA in
   I2C_TRISTATE. It should be enough to set SDA high since
   its open drain.

 Jocke
> 
> Either way, I don't think we should preclude the use of SOFT I2C on
> Freescale CPUs.