[U-Boot-Users] [DNX#2006102042000014] [PATCH] Add Marvell Phy and RGMII support to eTSEC [...]
DENX Support System
support at denx.de
Fri Oct 20 09:10:02 CEST 2006
Hello list,
inside the automatic U-Boot patch tracking system a new ticket
[DNX#2006102042000014] was created:
<snip>
>
> This sets up the eTSEC and the Marvel Phy to support
> 10M, 100M and 1000M rates when configured in RGMII
> mode.
>
> CHANGELOG:
>
> * Add eTSEC support for RGMII mode 10M, 100M & 1000M rates
>
> diff --git a/drivers/tsec.c b/drivers/tsec.c
> index 7ec565c..6cc6444 100644
> --- a/drivers/tsec.c
> +++ b/drivers/tsec.c
> @@ -583,11 +583,10 @@ static void adjust_link(struct eth_devic
> regs->maccfg2 =
> ((regs->maccfg2&~(MACCFG2_IF))
> | MACCFG2_MII);
>
> - /* If We're in reduced mode, we need
> - * to say whether we're 10 or 100 MB.
> + /* Set R100 bit in all modes although
> + * it is only used in RGMII mode
> */
> - if ((priv->speed == 100)
> - && (priv->flags & TSEC_REDUCED))
> + if (priv->speed == 100)
> regs->ecntrl |= ECNTRL_R100;
> else
> regs->ecntrl &= ~(ECNTRL_R100);
> @@ -785,6 +784,7 @@ struct phy_info phy_info_M88E1111S = {
> {0x1d, 0x5, NULL},
> {0x1e, 0x0, NULL},
> {0x1e, 0x100, NULL},
> + {0x14, 0x0cd2, NULL}, /* Add delay to RGMII TX and RX */
> {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
> {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
> {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
> --
> 1.4.2.3
</snip>
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