[U-Boot-Users] debugging u-boot

Lei Sun leisun124 at gmail.com
Fri Oct 20 19:19:54 CEST 2006


Hi Ben:
  Thanks for the tips!
  We didn't use local bus interface to flash, but used 60x bus
instead. I looked at the schematic and did found some difference
between SDK (PQ2FADS-VR) and our board. We used JS28T256P30N95 flash,
and connect all address pins to CPU's ADD pins, but the SDK use
BADDR[27-29] to connect to flash's A[2] - A[0].
According to the mpc82xx manul, that should be the right way.
  That's so weird, because i was able to read the correct content out
of the flash, after manually initialized the BR/OR register through
JTAG.  It shouldn't be working at all if the flash connection was
wrong somehow.

Thanks

On 10/20/06, Ben Warren <bwarren at qstreams.com> wrote:
> On Fri, 2006-10-20 at 10:55 -0400, Lei Sun wrote:
> > Hi all:
> >   I am trying to bring up a custom designed board based on MPC8270,
> > after spent 3 weeks on fixing hardware issues (extreme surgery !) , I
> > finally be able to read something out of the flash and verified SDRAM
> > is working as well. Up to this point our JTAG debugger is dead! I
> > burned u-boot Image using a programmer and put it in. after power up
> > and did a PORESET, I found out that every 20 seconds or so , system
> > generated HRESET,( by measuring the HRESET pin of the JTAG port). It
> > does read Hardware Reset Config Word when reset happens (I saw pulse
> > on the CS0 pin).  Before the JTAG die, i was able to issue "reset"
>
> Just because CS0 pulses, it doesn't mean the RCW was read successfully.
> Look in your CPU's manual, but I think the 20-second periodic reset
> means it wasn't read properly.  Check that your local bus interface to
> the flash is identical to a known working design, for example the
> Freescale evaluation boards (Schematics should be available on their
> website).  Pay close attention to the LS address bits, which, at least
> on the MPC8349, should use the dedicated address signals (LA27-LA31) and
> not the muxed ones(LAD27-LAD31).  Again, check against a reference
> design just to be sure.
>
> > 2. Any good JTAG debugger for this family of CPU you can recommend ?
> As others have mentioned, the Abatron BDI-2000 is excellent.
>
> regards,
> Ben
>
>




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