[U-Boot-Users] (MIPS) Cache behaviour

[Hans Zuidam]

Hi,

I am implementing cache control for our MIPS cores and ran into a couple 
of questions.

        o Should dcache_disable() also flush the (data) cache?
        some implementations do (e.g. ppc4xx) and some (e.g. mips) 
don't...

        o What is the difference between flush and invalidate?
        does flush mean invalidate with write-back and invalidate only
        invalidates the cache contents?

        o Which cache functions should be implemented?
        [di]cache_(dis|en)able, [di]cache_status, [di]cache_flush, more?

The cores are largely 4K/4Kc compatible, which are in turn MIPS32 
compatible.  The
cache implementation is therefore basically applicable for every MIPS32 
compatible
core.

Regards,
Hans Zuidam
--
Hans Zuidam
Sen. Systems Engineer, BL DTS ICE, Philips Semiconductors

Building A410, Room 3.40
High Tech Campus 41, 5656 AE Eindhoven, The Netherlands
Tel. +31 (0)40 2746579
E-Mail: hans.zuidam at philips.com