[U-Boot-Users] SystemACE

[Michal Simek]

Hi,
I have debugged systemace driver and ported it on Microblaze. I use 
SystemACE for loading bitstream to FPGA. But if the SystemACE initializes 
FPGA this part of code sets to zero CFGDONE bit in STATUSREG. And then 
release_cf_lock function resets SystemACE.
I add this part of code to microblaze-git repository. Please test it if you 
can.

Best regards,
Michal Simek

+/*
+ * For FPGA configuration via SystemACE is reset unacceptable
+ * CFGDONE bit in STATUSREG is not set to 1.
+ */

+#ifndef SYSTEMACE_CONFIG_FPGA
                /* Reset the configruation controller */
                val = ace_readw(0x18);
                val |= 0x0080;
                ace_writew(val, 0x18);
+#endif

                retry = trans * 16;
                while (retry > 0) {