[U-Boot-Users] BDI2000 problems flashing virgin custom 8548board

[robert lazarski]

On 8/30/07, Swarthout Edward L-SWARTHOU <ed.swarthout at freescale.com> wrote:
> From: robert lazarski
> >
> > Which manual? I tried
>
> See Chapter 2. "Memory map" and "4.4.3.3 Boot ROM Location" in:
>
> http://www.freescale.com/files/32bit/doc/ref_manual/MPC8548ERM.pdf
>
> Without the BDI configuration, you get a 8M window to the boot device
> of your choice.  This is controlled by three configuration pins.
>
> You also get a 1M window into the configuration space at ff70_0000.
> This typically is moved to e000_0000 in u-boot.
>
> -EdS
>

Another day all, thanks for helping.

Here's what we don't understand about the manual and the CDS example
in respect to our flash - both I and the hardware engineer are in
doubt here.  In Table 2-8. LAWARn we have for bits 8-11:

0000 PCI1/PCI-X
0001 PCI2
0010 PCI Express
0011 Reserved
0100 Local bus memory controller
0101–1011Reserved
1100 RapidIO
1101–1110Reserved
1111 DDR SDRAM

So what we see is that the CDS example is putting 1GB on the local bus
- is this for the flash?

WM32    0xe0000C28      0x000c0000      ;LAWBAR0 : @0xc0000000
WM32    0xe0000C30      0x8040001d      ;LAWAR0  : Local Bus  1GB

Do we have to assign a LAW to our flash in order to write to it? Ben
suggested assigning a LAW from 0xf8000000 to 0xffffffff (our 128MB
flash) . How would we go about doing that on the 8548 ? We tried:

WM32    0xe0000C08      0xF8000000      ;LAWBAR0 : @0xc0000000
WM32    0xe0000C10      0x8040001d      ;LAWAR0  : Local Bus  1GB

atum>mdh 0xf8000000
# SAP: read access failed

Here's the current config we are trying to use, please help!

;bdiGDB configuration file for  Atum's 8548A
;---------------------------------------------------
;
[INIT]
;
; use the following two lines for STARTUP HALT
WSPR    63              0xffff0000      ;IVPR to boot core
WSPR    415             0x0000f000      ;IVOR15 : Debug exception
;
;
;================= setup for flash programming ===============
; Move CCSRBAR to 0xe0000000
WM32    0xff700000      0x000e0000      ;CCSRBAR to 0xe0000000
;
; Initialize LAWBAR's
WM32    0xe0000C08      0x000c0000      ;LAWBAR1 : @0xc0000000
WM32    0xe0000C10      0x8040001d      ;LAWAR1  : Local Bus  1GB
;
; Setup Flash chip select
WM32    0xe0005000      0xf8001001      ;BR0
WM32    0xe0005004      0xf8006E65      ;OR0

; Enable flash programming
WM16 0xfe000000 0x0060 ;clear flash lock-bits
WM16 0xfe000000 0x00d0
DELAY 1000
WM16 0xfe000000 0xffff
;

;================= end flash programming =====================
;


[TARGET]
CPUTYPE     8548        ;the CPU type
JTAGCLOCK   0           ;use 16 MHz JTAG clock
;STARTUP     STOP 5000   ;let U-boot code setup the system
STARTUP     HALT        ;halt core while HRESET is asserted
BREAKMODE   HARD      	;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODE    HWBP        ;JTAG or HWBP, HWBP uses a hardware breakpoint
WAKEUP      500         ;give reset time to complete
POWERUP     5000        ;start delay after power-up detected in ms


[HOST]
IP          10.101.43.10
FILE        vmlinux.8548
FORMAT      ELF
LOAD        MANUAL              ;load code MANUAL or AUTO after reset
DUMP        dump
PROMPT      3ep8548a>


[FLASH]
CHIPTYPE    MIRRORX16   ;S29GL01GP
CHIPSIZE    0x8000000    ;The size of one flash chip in bytes - 1Gb
BUSWIDTH    16          ;The width of the flash memory bus in bits (8 | 16 | 32)
FILE        u-boot.bin
FORMAT      BIN 0xF8000000
ERASE       0xF8000000          ;erase sector 0


[REGS]
FILE        $reg8548.def