[U-Boot-Users] PPC440EPx: Make Sequoia boot vxWorks
Niklaus Giger
niklausgiger at gmx.ch
Wed Dec 5 08:16:56 CET 2007
vxWorks expects in
TLB 0 a entry for the Machine Check interrupt
TLB 1 a entry for the RAM
TLB 2 a entry for the EBC
TLB 3 a entry for the boot flash
Therefore I reordered the TLB entries correspondingly and did set the
CFG_TLB_FOR_BOOT_FLASH to 3 (see my previous patch about minimal
support for vxWorks)
After changing the baudrate to 9600 I had no problems to boot the
vxWorks image as distributed by WindRiver (Revision 2.0/1 from
June 18, 2007)
Signed-off-by: Niklaus Giger <niklaus.giger at netstal.com>
---
Hi Stefan
I have no problems about nitpicking, as it helps me to learn how to work
efficiently with you maintainers. I really appreciate your work. Therefore
I hope I got at least this third attempt right.
board/amcc/sequoia/init.S | 20 ++++++++++----------
include/configs/sequoia.h | 1 +
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S
index 5fe3af9..21ee9f5 100644
--- a/board/amcc/sequoia/init.S
+++ b/board/amcc/sequoia/init.S
@@ -87,19 +87,22 @@
tlbtab:
tlbtab_start
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
- * speed up boot process. It is patched after relocation to enable SA_I
- */
+ /* vxWorks needs this as first entry for the Machine Check interrupt */
+ tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for DDR SDRAM (Up to 2GB) */
+ tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for EBC */
+ tlbentry( CFG_BCSR_BASE, SZ_256M, CFG_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the */
#ifndef CONFIG_NAND_SPL
tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
#else
tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
#endif
- /* TLB-entry for DDR SDRAM (Up to 2GB) */
- tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-
#ifdef CFG_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
@@ -111,9 +114,6 @@ tlbtab:
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
- /* TLB-entry for EBC */
- tlbentry( CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
-
/* TLB-entry for NAND */
tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 600f98c..6a972e4 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -53,6 +53,7 @@
#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+#define CFG_TLB_FOR_BOOT_FLASH 3
#define CFG_BOOT_BASE_ADDR 0xf0000000
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
--
1.5.2
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