[U-Boot-Users] [PATCH 1/2] mpc85xx: Add support for ATUM8548
robert lazarski
robertlazarski at gmail.com
Thu Dec 20 23:40:04 CET 2007
Add support for Instituto Atlantico's ATUM8548 board
Signed-off-by: robert lazarski <robertlazarski at gmail.com>
diff --git a/MAINTAINERS b/MAINTAINERS
index b8c1fdc..5455a71 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -217,6 +217,10 @@ Thomas Lange <thomas at corelatus.se>
GTH MPC860
+Robert Lazarski <robertlazarski at gmail.com>
+
+ ATUM8548 MPC8548
+
The LEOX team <team at leox.org>
ELPT860 MPC860T
diff --git a/MAKEALL b/MAKEALL
index a02412b..45db9b8 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -317,6 +317,7 @@ LIST_83xx=" \
#########################################################################
LIST_85xx=" \
+ ATUM8548 \
MPC8540ADS \
MPC8540EVAL \
MPC8541CDS \
diff --git a/Makefile b/Makefile
index bde38ca..4f02421 100644
--- a/Makefile
+++ b/Makefile
@@ -1910,6 +1910,9 @@ TQM834x_config: unconfig
## MPC85xx Systems
#########################################################################
+ATUM8548_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548
+
MPC8540ADS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads freescale
diff --git a/board/atum8548/u-boot.lds b/board/atum8548/u-boot.lds
new file mode 100644
index 0000000..5c0e8a2
--- /dev/null
+++ b/board/atum8548/u-boot.lds
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ board/atum8548/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc85xx/start.o (.text)
+ board/atum8548/init.o (.text)
+ cpu/mpc85xx/traps.o (.text)
+ cpu/mpc85xx/interrupts.o (.text)
+ cpu/mpc85xx/cpu_init.o (.text)
+ cpu/mpc85xx/cpu.o (.text)
+ cpu/mpc85xx/speed.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/doc/README.atum8548 b/doc/README.atum8548
new file mode 100644
index 0000000..4eb56ba
--- /dev/null
+++ b/doc/README.atum8548
@@ -0,0 +1,29 @@
+Building U-Boot
+---------------
+
+The ATUM8548 code is known to build using ELDK 4.1.
+
+$ make ATUM8548_config
+Configuring for ATUM8548 board...
+$ make
+
+Using Flash
+-----------
+
+The ATUM8548 board has one flash bank, of 128MB in size (2^23 = 0x08000000).
+
+The BDI2000 commands for copying u-boot into flash are
+as follows:
+
+ erase 0xFFF80000 0x4000 0x20
+ prog 0xfff80000 uboot.bin bin
+
+Booting Linux
+-------------
+
+U-boot/kermit commands for booting linux via NFS - assumming the proper
+bootargs are set - are as follows:
+
+ tftp 1000000 uImage.atum
+ tftp c00000 mpc8548atum.dtb
+ bootm 1000000 - c00000
diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h
new file mode 100644
index 0000000..bd09380
--- /dev/null
+++ b/include/configs/ATUM8548.h
@@ -0,0 +1,582 @@
+/*
+ * Copyright 2007
+ * Robert Lazarski, Instituto Atlantico, robertlazarski at gmail.com
+ *
+ * Copyright 2004, 2007 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * atum8548 board configuration file
+ *
+ * Please refer to doc/README.atum8548 for more info.
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Debug Options, Disable in production
+#define ET_DEBUG 1
+#define CONFIG_PANIC_HANG 1
+#define DEBUG 1
+*/
+
+/* CPLD Configuration Options */
+#define MPC85xx_ATUM_CLKOCR 0x80000002
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE 1 /* BOOKE */
+#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548 1 /* MPC8548 specific */
+
+#define CONFIG_PCI 1 /* enable any pci type devices */
+#define CONFIG_PCI1 1 /* PCI controller 1 */
+#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
+#define CONFIG_PCI2 1 /* PCI controller 2 */
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+
+#define CONFIG_TSEC_ENET 1 /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for DDR setup*/
+#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+
+#define CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
+
+#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
+
+#define CONFIG_SYS_CLK_FREQ 33000000
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS 1
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+
+#define CONFIG_CMD_SDRAM 1 /* SDRAM DIMM SPD info printout */
+#define CONFIG_ENABLE_36BIT_PHYS 1
+#undef CFG_DRAM_TEST
+#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
+#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+
+#define PCI_SPEED 33333000 /* CPLD currenlty does not have
PCI setup info */
+#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
+#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
+#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+/*
+ * Disable instruction cache, used to verify problems with certain chips
+ * until the problems have been fully resolved in a future revision
+ */
+#define DISABLE_ICACHE /* Disable instruction cache */
+
+#if defined(CONFIG_SPD_EEPROM)
+ /*
+ * Determine DDR configuration from I2C interface.
+ */
+ #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
+
+#else
+ /*
+ * Manually set up DDR parameters
+ */
+ #define CFG_SDRAM_SIZE 1024 /* DDR is 1024MB */
+ #define CFG_DDR_CS0_BNDS 0x0000000f /* 0-1024 */
+ #define CFG_DDR_CS0_CONFIG 0x80000102
+ #define CFG_DDR_TIMING_0 0x00260802
+ #define CFG_DDR_TIMING_1 0x38355322
+ #define CFG_DDR_TIMING_2 0x039048c7
+ #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
+ #define CFG_DDR_MODE 0x00000432
+ #define CFG_DDR_INTERVAL 0x05150100
+ #define DDR_SDRAM_CFG 0x43000000
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * FLASH on the Local Bus
+ * based on flash chip S29GL01GP
+ * One bank, 128M, using the CFI driver.
+ * Boot from BR0 bank at 0xf800_0000
+ *
+ * BR0:
+ * Base address 0 = 0xF8000000 = BR0[0:16] = 1111 1000 0000 0000 0
+ * Port Size = 16 bits = BRx[19:20] = 10
+ * Use GPCM = BRx[24:26] = 000
+ * Valid = BRx[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1000 0000 0000 0001 0000 0000 0001 = f8001001 BR0
+ *
+ * OR0:
+ * Addr Mask = 128M = ORx[0:16] = 1111 1000 0000 0000 0
+ * Reserved ORx[17:18] = 00
+ * CSNT = ORx[20] = 1
+ * ACS = half cycle delay = ORx[21:22] = 11
+ * SCY = 6 = ORx[24:27] = 0110
+ * TRLX = use relaxed timing = ORx[29] = 1
+ * EAD = use external address latch delay = OR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1000 0000 0000 0000 1110 0110 0101 = f8000E65 ORx
+ */
+
+#define CFG_BOOT_BLOCK 0xf8000000 /* boot TLB block */
+#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 128M */
+
+#define CFG_BR0_PRELIM 0xf8001001
+
+#define CFG_OR0_PRELIM 0xf8000E65
+
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 512000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT 8000 /* Flash Write Timeout (ms) */
+
+
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#define CFG_FLASH_CFI_DRIVER 1
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_EMPTY_INFO
+
+/*
+ * Flash on the LocalBus
+ */
+#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
+
+/* Memory */
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+
+#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE 8192
+
+#define OF_CPU "PowerPC,8548 at 0"
+#define OF_SOC "soc8548 at e0000000"
+#define OF_TBCLK (bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH "/soc8548 at e0000000/serial at 4600"
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_EEPROM_ADDR 0x57
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */
+
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI1_IO_BASE 0x00000000
+#define CFG_PCI1_IO_PHYS 0xe2000000
+#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
+
+#ifdef CONFIG_PCI2
+#define CFG_PCI2_MEM_BASE 0xC0000000
+#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI2_IO_BASE 0x00000000
+#define CFG_PCI2_IO_PHYS 0xe2800000
+#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
+#endif
+
+#ifdef CONFIG_PCIE1
+#define CFG_PCIE1_MEM_BASE 0xa0000000
+#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
+#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCIE1_IO_BASE 0x00000000
+#define CFG_PCIE1_IO_PHYS 0xe3000000
+#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
+#endif
+
+
+#if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR 0xe0000000
+ #define PCI_ENET0_MEMADDR 0xe0000000
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+#endif
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS 0x00000000
+#define CFG_PCI_MEMORY_PHYS 0x00000000
+#define CFG_PCI_MEMORY_SIZE 0x80000000
+
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC1"
+#define CONFIG_TSEC3 1
+#define CONFIG_TSEC3_NAME "eTSEC2"
+#define CONFIG_TSEC4 1
+#define CONFIG_TSEC4_NAME "eTSEC3"
+#undef CONFIG_MPC85XX_FEC
+
+#define TSEC1_PHY_ADDR 0
+#define TSEC2_PHY_ADDR 1
+#define TSEC3_PHY_ADDR 2
+#define TSEC4_PHY_ADDR 3
+
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC3_PHYIDX 0
+#define TSEC4_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+#define TSEC3_FLAGS TSEC_GIGABIT
+#define TSEC4_FLAGS TSEC_GIGABIT
+
+/* Options are: eTSEC[0-3] */
+#define CONFIG_ETHPRIME "eTSEC2"
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+#define CFG_ENV_SIZE 0x2000
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+
+#if defined(CONFIG_PCI)
+ #define CONFIG_CMD_PCI
+#endif
+
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
+#endif
+
+#define CONFIG_IPADDR 10.101.43.142
+
+#define CONFIG_HOSTNAME atum
+#define CONFIG_ROOTPATH /nfsroot
+#define CONFIG_BOOTFILE /tftpboot/uImage.atum
+#define CONFIG_UBOOTPATH /tftpboot/uboot.bin /* TFTP server */
+
+#define CONFIG_SERVERIP 10.101.43.10
+#define CONFIG_GATEWAYIP 10.101.45.1
+#define CONFIG_NETMASK 255.255.248.0
+
+#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
+
+#define CONFIG_BAUDRATE 115200
+
+#if defined(CONFIG_PCIE1)
+#define PCIE_ENV \
+ "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
+ "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
+ "pcieerr=md ${a}020 1; md ${a}e00 e; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
+ "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
+ "pci d $b.0 130 1\0" \
+ "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;" \
+ "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;"\
+ "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
+ "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
+ "pcie1regs=setenv a e000a; run pciereg\0" \
+ "pcie1cfg=setenv b 3; run pciecfg\0" \
+ "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \
+ "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0"
+#else
+#define PCIE_ENV ""
+#endif
+
+#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
+#define PCI_ENV \
+ "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
+ "echo e;md ${a}e00 9\0" \
+ "pcierr=md ${a}e00 8; pci d.b $b.0 7 1;pci d.w $b.0 1e 1;" \
+ "pci d.w $b.0 56 1\0" \
+ "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \
+ "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0"
+#else
+#define PCI_ENV ""
+#endif
+
+#if defined(CONFIG_PCI1)
+#define PCI_ENV1 \
+ "pci1regs=setenv a e0008; run pcireg\0" \
+ "pci1err=setenv a e0008; setenv b 0; run pcierr\0" \
+ "pci1errc=setenv a e0008; setenv b 0; run pcierrc\0"
+#else
+#define PCI_ENV1 ""
+#endif
+
+#if defined(CONFIG_PCI2)
+#define PCI_ENV2 \
+ "pci2regs=setenv a e0009; run pcireg\0" \
+ "pci2err=setenv a e0009; setenv b 123; run pcierr\0" \
+ "pci2errc=setenv a e0009; setenv b 123; run pcierrc\0"
+#else
+#define PCI_ENV2 ""
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+#define ENET_ENV \
+ "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \
+ "md ${a}098 2\0" \
+ "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \
+ "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \
+ "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \
+ "echo mib;md ${a}680 31\0" \
+ "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \
+ "enet1regs=setenv a e0024; run enetreg\0" \
+ "enet2regs=setenv a e0025; run enetreg\0" \
+ "enet3regs=setenv a e0026; run enetreg\0" \
+ "enet4regs=setenv a e0027; run enetreg\0"
+#else
+#define ENET_ENV ""
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth2\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "ethact=eTSEC2\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=ramdisk.uboot\0" \
+ "dtbaddr=c00000\0" \
+ "dtbfile=mpc8548atum.dtb\0" \
+ "eoi=mw e00400b0 0\0" \
+ "iack=md e00400a0 1\0" \
+ "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md
${a}bf0 4;" \
+ "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
+ "ddrregs=setenv a e0002; run ddrreg\0" \
+ "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
+ "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
+ "guregs=setenv a e00e0; run gureg\0" \
+ "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
+ "ecmregs=setenv a e0001; run ecmreg\0" \
+ "lawregs=md e0000c08 4b\0" \
+ "lbcregs=md e0005000 36\0" \
+ "dma0regs=md e0021100 12\0" \
+ "dma1regs=md e0021180 12\0" \
+ "dma2regs=md e0021200 12\0" \
+ "dma3regs=md e0021280 12\0" \
+ PCIE_ENV \
+ PCI_ENV \
+ PCI_ENV1 \
+ PCI_ENV2 \
+ ENET_ENV
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr - $dtbaddr"
+
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr $ramdiskaddr $dtbaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif /* __CONFIG_H */
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