[U-Boot-Users] [PATCH 2/2] Bit-bang implementation of 802.3ae MII-PHY framing

[Ben Warren]

Hello,

This implements 'IEEE 802.3ae clause 25' on the bit-bang MII-PHY driver.
 
Signed-off-by: Ben Warren <bwarren at .qstreams.com>
---
 common/miiphybb.c |  121 +++++++++++++++++++++++++++++++++++++++++------------
 include/miiphy.h  |    4 ++
 2 files changed, 98 insertions(+), 27 deletions(-)

diff --git a/common/miiphybb.c b/common/miiphybb.c
index 537c15d..296da7f 100644
--- a/common/miiphybb.c
+++ b/common/miiphybb.c
@@ -29,19 +29,30 @@
 #include <common.h>
 #include <ioports.h>
 #include <ppc_asm.tmpl>
+#include <miiphy.h>
 
 #ifdef CONFIG_BITBANGMII
 
+#define OPCODE_BIT_0		0x01
+#define OPCODE_BIT_1		0x02
 
+#define OPCODE_ADDRESS		0x00
+#define OPCODE_WRITE		OPCODE_BIT_0
+#define OPCODE_READ		OPCODE_BIT_1
+#define OPCODE_READ_FIXED	(OPCODE_BIT_0 | OPCODE_BIT_1)
+
+#define START_BIT_0		0x10
+#define START_BIT_1		0x20
 /*****************************************************************************
  *
  * Utility to send the preamble, address, and register (common to read
  * and write).
  */
-static void miiphy_pre (char read, unsigned char addr, unsigned char reg)
+static void miiphy_pre(unsigned char ops, unsigned char addr, 
+		unsigned char reg)
 {
 	int j;			/* counter */
-#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
+#if defined(MDIO_PORT)
 	volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
 #endif
 
@@ -62,24 +73,24 @@ #endif
 		MIIDELAY;
 	}
 
-	/* send the start bit (01) and the read opcode (10) or write (10) */
+	/* send the start bits and the opcode */
 	MDC (0);
-	MDIO (0);
+	MDIO ((ops & START_BIT_1 ? 1 : 0));
 	MIIDELAY;
 	MDC (1);
 	MIIDELAY;
 	MDC (0);
-	MDIO (1);
+	MDIO ((ops & START_BIT_0 ? 1 : 0));
 	MIIDELAY;
 	MDC (1);
 	MIIDELAY;
 	MDC (0);
-	MDIO (read);
+	MDIO ((ops & OPCODE_BIT_1) ? 1 : 0);
 	MIIDELAY;
 	MDC (1);
 	MIIDELAY;
 	MDC (0);
-	MDIO (!read);
+	MDIO ((ops & OPCODE_BIT_0) ? 1 : 0);
 	MIIDELAY;
 	MDC (1);
 	MIIDELAY;
@@ -114,24 +125,14 @@ #endif
 }
 
 
-/*****************************************************************************
- *
- * Read a MII PHY register.
- *
- * Returns:
- *   0 on success
- */
-int bb_miiphy_read (char *devname, unsigned char addr,
-		unsigned char reg, unsigned short *value)
+static int _bb_miiphy_read(unsigned short *value)
 {
 	short rdreg;		/* register working value */
 	int j;			/* counter */
-#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
+#if defined(MDIO_PORT)
 	volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
 #endif
 
-	miiphy_pre (1, addr, reg);
-
 	/* tri-state our MDIO I/O pin so we can read */
 	MDC (0);
 	MDIO_TRISTATE;
@@ -181,24 +182,52 @@ #endif
 	return 0;
 }
 
+/*****************************************************************************
+ *
+ * Read a MII PHY register.
+ *
+ * Returns:
+ *   0 on success
+*****************************************************************************/
+
+int bb_miiphy_read (char *devname, unsigned char addr,
+		unsigned char reg, unsigned short *value)
+{
+	unsigned char ops;
+
+	ops = (miiphy_get_flags(devname) & MII_FLAG_802_3ae) ? 
+					0x00 : START_BIT_0;
+	ops |= OPCODE_READ;
+	miiphy_pre (ops, addr, reg);
+	return _bb_miiphy_read(value);
+}
 
 /*****************************************************************************
  *
- * Write a MII PHY register.
+ * Non-incrementing read
  *
  * Returns:
  *   0 on success
- */
-int bb_miiphy_write (char *devname, unsigned char addr,
-		unsigned char reg, unsigned short value)
+*****************************************************************************/
+
+int bb_miiphy_read_fixed(char *devname, unsigned char addr,
+		unsigned char reg, unsigned short *value)
+{
+	unsigned char ops;
+
+	ops = (miiphy_get_flags(devname) & MII_FLAG_802_3ae) ? 
+					0x00 : START_BIT_0;
+	ops |= OPCODE_READ_FIXED;
+	miiphy_pre (ops, addr, reg);
+	return _bb_miiphy_read(value);
+}
+
+static int _bb_miiphy_write(unsigned short value)
 {
 	int j;			/* counter */
-#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
+#if defined(MDIO_PORT)
 	volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
 #endif
-
-	miiphy_pre (0, addr, reg);
-
 	/* send the turnaround (10) */
 	MDC (0);
 	MDIO (1);
@@ -237,4 +266,42 @@ #endif
 	return 0;
 }
 
+/*****************************************************************************
+ *
+ * Write a MII PHY register.
+ *
+ * Returns:
+ *   0 on success
+*****************************************************************************/
+int bb_miiphy_write (char *devname, unsigned char addr,
+		unsigned char reg, unsigned short value)
+{
+	unsigned char ops;
+
+	ops = (miiphy_get_flags(devname) & MII_FLAG_802_3ae) ? 
+					0x00 : START_BIT_0;
+	ops |= OPCODE_WRITE;
+	miiphy_pre (ops, addr, reg);
+	return _bb_miiphy_write(value);
+}
+
+/*****************************************************************************
+ *
+ * Perform 'address' function
+ *
+ * Returns:
+ *   0 on success
+*****************************************************************************/
+int bb_miiphy_address (char *devname, unsigned char addr,
+		unsigned char reg, unsigned short value)
+{
+	unsigned char ops;
+
+	ops = (miiphy_get_flags(devname) & MII_FLAG_802_3ae) ? 
+					0x00 : START_BIT_0;
+	ops |= OPCODE_ADDRESS;
+	miiphy_pre (ops, addr, reg);
+	return _bb_miiphy_write(value);
+}
+
 #endif /* CONFIG_BITBANGMII */
diff --git a/include/miiphy.h b/include/miiphy.h
index 9e7e35f..86ffbb5 100644
--- a/include/miiphy.h
+++ b/include/miiphy.h
@@ -98,6 +98,10 @@ int bb_miiphy_read (char *devname, unsig
 		unsigned char reg, unsigned short *value);
 int bb_miiphy_write (char *devname, unsigned char addr,
 		unsigned char reg, unsigned short value);
+int bb_miiphy_address (char *devname, unsigned char addr,
+		unsigned char reg, unsigned short value);
+int bb_miiphy_read_fixed (char *devname, unsigned char addr,
+		unsigned char reg, unsigned short *value);
 
 /* phy seed setup */
 #define AUTO			99
-- 
1.4.1