[U-Boot-Users] [DNX#2007012342000024] [PATCH 2/2] Bit-bang implementation of 802.3ae MII [...]

[OTRS Notification Master]

Hello list,

inside the automatic U-Boot patch tracking system a new ticket
[DNX#2007012342000024] was created:

<snip>
> Hello,
> 
> This implements 'IEEE 802.3ae clause 25' on the bit-bang MII-PHY driver.
>  
> Signed-off-by: Ben Warren <bwarren at .qstreams.com>
> ---
>  common/miiphybb.c |  121
> +++++++++++++++++++++++++++++++++++++++++------------
>  include/miiphy.h  |    4 ++
>  2 files changed, 98 insertions(+), 27 deletions(-)
> 
> diff --git a/common/miiphybb.c b/common/miiphybb.c
> index 537c15d..296da7f 100644
> --- a/common/miiphybb.c
> +++ b/common/miiphybb.c
> @@ -29,19 +29,30 @@
>  #include <common.h>
>  #include <ioports.h>
>  #include <ppc_asm.tmpl>
> +#include <miiphy.h>
>  
>  #ifdef CONFIG_BITBANGMII
>  
> +#define OPCODE_BIT_0		0x01
> +#define OPCODE_BIT_1		0x02
>  
> +#define OPCODE_ADDRESS		0x00
> +#define OPCODE_WRITE		OPCODE_BIT_0
> +#define OPCODE_READ		OPCODE_BIT_1
> +#define OPCODE_READ_FIXED	(OPCODE_BIT_0 | OPCODE_BIT_1)
> +
> +#define START_BIT_0		0x10
> +#define START_BIT_1		0x20
>  /*****************************************************************************
>   *
>   * Utility to send the preamble, address, and register (common to read
>   * and write).
>   */
> -static void miiphy_pre (char read, unsigned char addr, unsigned char
> reg)
> +static void miiphy_pre(unsigned char ops, unsigned char addr, 
> +		unsigned char reg)
>  {
>  	int j;			/* counter */
> -#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
> +#if defined(MDIO_PORT)
>  	volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR,
> MDIO_PORT);
>  #endif
>  
> @@ -62,24 +73,24 @@ #endif
>  		MIIDELAY;
>  	}
>  
> -	/* send the start bit (01) and the read opcode (10) or write (10) */
> +	/* send the start bits and the opcode */
>  	MDC (0);
> -	MDIO (0);
> +	MDIO ((ops & START_BIT_1 ? 1 : 0));
>  	MIIDELAY;
>  	MDC (1);
>  	MIIDELAY;
>  	MDC (0);
> -	MDIO (1);
> +	MDIO ((ops & START_BIT_0 ? 1 : 0));
>  	MIIDELAY;
>  	MDC (1);
>  	MIIDELAY;
>  	MDC (0);
> -	MDIO (read);
> +	MDIO ((ops & OPCODE_BIT_1) ? 1 : 0);
>  	MIIDELAY;
>  	MDC (1);
>  	MIIDELAY;
>  	MDC (0);
> -	MDIO (!read);
> +	MDIO ((ops & OPCODE_BIT_0) ? 1 : 0);
>  	MIIDELAY;
>  	MDC (1);
>  	MIIDELAY;
> @@ -114,24 +125,14 @@ #endif
>  }
>  
>  
> -/*****************************************************************************
> - *
> - * Read a MII PHY register.
> - *
> - * Returns:
> - *   0 on success
> - */
> -int bb_miiphy_read (char *devname, unsigned char addr,
> -		unsigned char reg, unsigned short *value)
> +static int _bb_miiphy_read(unsigned short *value)
>  {
>  	short rdreg;		/* register working value */
>  	int j;			/* counter */
> -#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
> +#if defined(MDIO_PORT)
>  	volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR,
</snip>

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