[U-Boot-Users] Please pull from 'mpc83xx' branch

Kumar Gala galak at kernel.crashing.org
Tue Jan 30 22:34:54 CET 2007


Please pull from 'mpc83xx' branch of
git://git.kernel.org/pub/scm/boot/u-boot/galak/u-boot.git

to receive the following updates:

>From bec770f7708fde81e96eec3230851c04f8b822db Mon Sep 17 00:00:00 2001
From: Kumar Gala <galak at kernel.crashing.org>
Date: Tue, 30 Jan 2007 14:08:30 -0600
Subject: [PATCH] Replace CONFIG_MPC8349 and use CONFIG_MPC834X instead

The code that is ifdef'd with CONFIG_MPC8349 is actually applicable to all
MPC834X class processors.  Change the protections from CONFIG_MPC8349 to
CONFIG_MPC834X so they are more generic.

Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
---
  cpu/mpc83xx/cpu.c             |    2 +-
  cpu/mpc83xx/speed.c           |    8 ++++----
  include/asm-ppc/global_data.h |    4 ++--
  include/asm-ppc/immap_83xx.h  |    2 +-
  include/mpc83xx.h             |   14 +++++++-------
  5 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index bc61219..15e04ba 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -113,7 +113,7 @@ int checkcpu(void)
  		return -1;	/* Not sure what this is */
  	}

-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
  	printf("Rev: %02x at %s MHz\n", (spridr & 0x0000FFFF)>>4 |(spridr & 0x0000000F), strmhz(buf, clock));
  #else
  	printf("Rev: %02x at %s MHz\n", spridr & 0x0000FFFF, strmhz(buf, clock));
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index 9fd1bf1..c759930 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -99,7 +99,7 @@ int get_clocks(void)
  	u32 lcrr;

  	u32 csb_clk;
-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
  	u32 tsec1_clk;
  	u32 tsec2_clk;
  	u32 usbmph_clk;
@@ -148,7 +148,7 @@ int get_clocks(void)

  	sccr = im->clk.sccr;

-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
  	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
  	case 0:
  		tsec1_clk = 0;
@@ -314,7 +314,7 @@ int get_clocks(void)
  #endif

  	gd->csb_clk = csb_clk;
-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
  	gd->tsec1_clk = tsec1_clk;
  	gd->tsec2_clk = tsec2_clk;
  	gd->usbmph_clk = usbmph_clk;
@@ -371,7 +371,7 @@ int print_clock_conf(void)
  #if !defined(CONFIG_MPC832X)
  	printf("  I2C2:                %4d MHz\n", gd->i2c2_clk / 1000000);
  #endif
-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
  	printf("  TSEC1:               %4d MHz\n", gd->tsec1_clk / 1000000);
  	printf("  TSEC2:               %4d MHz\n", gd->tsec2_clk / 1000000);
  	printf("  USB MPH:             %4d MHz\n", gd->usbmph_clk / 1000000);
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index 8bc61b6..c113b7e 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -52,12 +52,12 @@ typedef	struct	global_data {
  #if defined(CONFIG_MPC83XX)
  	/* There are other clocks in the MPC83XX */
  	u32 csb_clk;
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  	u32 tsec1_clk;
  	u32 tsec2_clk;
  	u32 usbmph_clk;
  	u32 usbdr_clk;
-#endif /* CONFIG_MPC8349 */
+#endif /* CONFIG_MPC834X */
  	u32 core_clk;
  	u32 i2c1_clk;
  	u32 i2c2_clk;
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index 77a079f..5e088d6 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -544,7 +544,7 @@ typedef struct security83xx {
  	u8 fixme[0x10000];
  } security83xx_t;

-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
  typedef struct immap {
  	sysconf83xx_t		sysconf;	/* System configuration */
  	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 52e4369..c1c6ad1 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -96,7 +96,7 @@
  #define SPCR_COREPR			0x00300000	/* E300 PowerPC Core system bus request priority */
  #define SPCR_COREPR_SHIFT		(31-11)

-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
  /* SPCR bits - MPC8349 specific */
  #define SPCR_TSEC1DP			0x00003000	/* TSEC1 data priority */
  #define SPCR_TSEC1DP_SHIFT		(31-19)
@@ -114,7 +114,7 @@

  /* SICRL/H - System I/O Configuration Register Low/High
   */
-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
  /* SICRL bits - MPC8349 specific */
  #define SICRL_LDP_A			0x80000000
  #define SICRL_USB1			0x40000000
@@ -340,7 +340,7 @@
  #define HRCWH_PCI_HOST_SHIFT		31
  #define HRCWH_PCI_AGENT			0x00000000

-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
  #define HRCWH_32_BIT_PCI		0x00000000
  #define HRCWH_64_BIT_PCI		0x40000000
  #endif
@@ -351,7 +351,7 @@
  #define HRCWH_PCI_ARBITER_DISABLE	0x00000000
  #define HRCWH_PCI_ARBITER_ENABLE	0x20000000

-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
  #define HRCWH_PCI2_ARBITER_DISABLE	0x00000000
  #define HRCWH_PCI2_ARBITER_ENABLE	0x10000000

@@ -375,14 +375,14 @@

  #define HRCWH_ROM_LOC_DDR_SDRAM		0x00000000
  #define HRCWH_ROM_LOC_PCI1		0x00100000
-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
  #define HRCWH_ROM_LOC_PCI2		0x00200000
  #endif
  #define HRCWH_ROM_LOC_LOCAL_8BIT	0x00500000
  #define HRCWH_ROM_LOC_LOCAL_16BIT	0x00600000
  #define HRCWH_ROM_LOC_LOCAL_32BIT	0x00700000

-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
  #define HRCWH_TSEC1M_IN_RGMII		0x00000000
  #define HRCWH_TSEC1M_IN_RTBI		0x00004000
  #define HRCWH_TSEC1M_IN_GMII		0x00008000
@@ -742,7 +742,7 @@
  #define BR_V				0x00000001
  #define BR_V_SHIFT			0

-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
  #define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
  #elif defined(CONFIG_MPC8360)
  #define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
-- 
1.4.4.2

>From 8fa0c664107f4dbce5f688c1c5c0f4f5f54a061c Mon Sep 17 00:00:00 2001
From: Kumar Gala <galak at kernel.crashing.org>
Date: Tue, 30 Jan 2007 15:23:48 -0600
Subject: [PATCH] Fix config of Arbiter, System Priority, and Clock Mode on MPC83xx

The config value for:
* CFG_ACR_PIPE_DEP
* CFG_ACR_RPTCNT
* CFG_SPCR_TSEC1EP
* CFG_SPCR_TSEC2EP
* CFG_SCCR_TSEC1CM
* CFG_SCCR_TSEC2CM

Were not being used when setting the appropriate register

Added:
* CFG_SCCR_USBMPHCM
* CFG_SCCR_USBDRCM
* CFG_SCCR_PCICM
* CFG_SCCR_ENCCM

To allow full config of the SCCR.

Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349
that were just bogus.

Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
---
  cpu/mpc83xx/cpu_init.c        |   33 +++++++++++++++++++++++++++------
  include/configs/MPC8349EMDS.h |   11 -----------
  include/configs/TQM834x.h     |   11 -----------
  include/configs/sbc8349.h     |   11 -----------
  include/mpc83xx.h             |    9 ++-------
  5 files changed, 29 insertions(+), 46 deletions(-)

diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index eb256e5..d01311d 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -69,31 +69,52 @@ void cpu_init_f (volatile immap_t * im)

  #ifdef CFG_ACR_PIPE_DEP
  	/* Arbiter pipeline depth */
-	im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (3 << ACR_PIPE_DEP_SHIFT);
+	im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
  #endif

  #ifdef CFG_SPCR_TSEC1EP
  	/* TSEC1 Emergency priority */
-	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (3 << SPCR_TSEC1EP_SHIFT);
+	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
  #endif

  #ifdef CFG_SPCR_TSEC2EP
  	/* TSEC2 Emergency priority */
-	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (3 << SPCR_TSEC2EP_SHIFT);
+	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
  #endif

+#ifdef CONFIG_MPC834X
  #ifdef CFG_SCCR_TSEC1CM
  	/* TSEC1 clock mode */
-	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (1 << SCCR_TSEC1CM_SHIFT);
+	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
  #endif
  #ifdef CFG_SCCR_TSEC2CM
  	/* TSEC2 & I2C1 clock mode */
-	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (1 << SCCR_TSEC2CM_SHIFT);
+	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
+#endif
+#ifdef CFG_SCCR_USBMPHCM
+	/* USB MPH clock mode */
+	im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) | (CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
+#endif
+#endif /* CONFIG_MPC834X */
+
+#ifdef CFG_SCCR_PCICM
+	/* PCI & DMA clock mode */
+	im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) | (CFG_SCCR_PCICM << SCCR_PCICM_SHIFT);
+#endif
+
+#ifdef CFG_SCCR_USBDRCM
+	/* USB DR clock mode */
+	im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) | (CFG_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
+#endif
+
+#ifdef CFG_SCCR_ENCCM
+	/* Encryption clock mode */
+	im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) | (CFG_SCCR_ENCCM << SCCR_PCICM_SHIFT);
  #endif

  #ifdef CFG_ACR_RPTCNT
  	/* Arbiter repeat count */
-	im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (3 << ACR_RPTCNT_SHIFT));
+	im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT));
  #endif

  	/* RSR - Reset Status Register - clear all status (4.6.1.3) */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 5bed2d0..d06b51d 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -60,17 +60,6 @@
  #endif
  #endif

-#define CFG_SCCR_INIT		(SCCR_DEFAULT & (~SCCR_CLK_MASK))
-#define CFG_SCCR_TSEC1CM	SCCR_TSEC1CM_1	/* TSEC1 clock setting */
-#define CFG_SCCR_TSEC2CM	SCCR_TSEC2CM_1	/* TSEC2 clock setting */
-#define CFG_SCCR_ENCCM		SCCR_ENCCM_3	/* ENC clock setting */
-#define CFG_SCCR_USBCM		SCCR_USBCM_3	/* USB clock setting */
-#define CFG_SCCR_VAL		( CFG_SCCR_INIT		\
-				| CFG_SCCR_TSEC1CM	\
-				| CFG_SCCR_TSEC2CM	\
-				| CFG_SCCR_ENCCM	\
-				| CFG_SCCR_USBCM	)
-
  #define CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */

  #define CFG_IMMR		0xE0000000
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 728083b..ed03577 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -57,17 +57,6 @@
   */
  #define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_8)

-#define CFG_SCCR_INIT		(SCCR_DEFAULT & (~SCCR_CLK_MASK))
-#define CFG_SCCR_TSEC1CM	SCCR_TSEC1CM_1	/* TSEC1 clock setting */
-#define CFG_SCCR_TSEC2CM	SCCR_TSEC2CM_1	/* TSEC2 clock setting */
-#define CFG_SCCR_ENCCM		SCCR_ENCCM_3	/* ENC clock setting */
-#define CFG_SCCR_USBCM		SCCR_USBCM_3	/* USB clock setting */
-#define CFG_SCCR_VAL		( CFG_SCCR_INIT		\
-				| CFG_SCCR_TSEC1CM	\
-				| CFG_SCCR_TSEC2CM	\
-				| CFG_SCCR_ENCCM	\
-				| CFG_SCCR_USBCM	)
-
  /* board pre init: do not call, nothing to do */
  #undef CONFIG_BOARD_EARLY_INIT_F

diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 1876c61..321d3ce 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -63,17 +63,6 @@
  #endif
  #endif

-#define CFG_SCCR_INIT		(SCCR_DEFAULT & (~SCCR_CLK_MASK))
-#define CFG_SCCR_TSEC1CM	SCCR_TSEC1CM_1	/* TSEC1 clock setting */
-#define CFG_SCCR_TSEC2CM	SCCR_TSEC2CM_1	/* TSEC2 clock setting */
-#define CFG_SCCR_ENCCM		SCCR_ENCCM_3	/* ENC clock setting */
-#define CFG_SCCR_USBCM		SCCR_USBCM_3	/* USB clock setting */
-#define CFG_SCCR_VAL		( CFG_SCCR_INIT		\
-				| CFG_SCCR_TSEC1CM	\
-				| CFG_SCCR_TSEC2CM	\
-				| CFG_SCCR_ENCCM	\
-				| CFG_SCCR_USBCM	)
-
  #undef CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */

  #define CFG_IMMR		0xE0000000
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index c1c6ad1..f1df5cf 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -498,6 +498,7 @@
  #define SCCR_PCICM_SHIFT		16

  /* SCCR bits - MPC8349 specific */
+#ifdef CONFIG_MPC834X
  #define SCCR_TSEC1CM			0xc0000000
  #define SCCR_TSEC1CM_SHIFT		30
  #define SCCR_TSEC1CM_0			0x00000000
@@ -511,6 +512,7 @@
  #define SCCR_TSEC2CM_1			0x10000000
  #define SCCR_TSEC2CM_2			0x20000000
  #define SCCR_TSEC2CM_3			0x30000000
+#endif

  #define SCCR_USBMPHCM			0x00c00000
  #define SCCR_USBMPHCM_SHIFT		22
@@ -522,13 +524,6 @@
  #define SCCR_USBCM_2			0x00A00000
  #define SCCR_USBCM_3			0x00F00000

-#define SCCR_CLK_MASK			( SCCR_TSEC1CM_3	\
-					| SCCR_TSEC2CM_3	\
-					| SCCR_ENCCM_3		\
-					| SCCR_USBCM_3		)
-
-#define SCCR_DEFAULT			0xFFFFFFFF
-
  /* CSn_BDNS - Chip Select memory Bounds Register
   */
  #define CSBNDS_SA			0x00FF0000
-- 
1.4.4.2





More information about the U-Boot mailing list