[U-Boot-Users] PPC assembler question for mpc8548cds

[robert lazarski]

On 7/2/07, Andy Fleming <afleming at gmail.com> wrote:
>
> On 6/26/07, robert lazarski <robertlazarski at gmail.com> wrote:
> > Hi all,
> >
> > What's confusing me is there is no constant BOOKE_PAGESZ_128M. For
> example,
> > the cds board has 128MB of SDRAM (my board has no SDRAM) . So the way
> the
> > cds code allocates the 128MB
> > for sdram is:
> >
> >          /*
> >          * TLB 6:       64M     Cacheable, non-guarded
> >          * 0xf000_0000  64M     LBC SDRAM
> >          */
> >         .long TLB1_MAS0(1, 6, 0)
> >         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
> >         .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE),
> > 0,0,0,0,0,0,0,0)
> >         .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE),
> > 0,0,0,0,0,1,0,1,0,1)
> >
> >
> > With LAW comments:
> >
> > * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
> >
>
>
> Ugh, that's awful.  It's a bug, and needs to be fixed.
>
>
> > I'm thinking this is because the TLB size can be allocated as 64MB for
> the
> > 128MB of flash, and then the LAW code needs to allocate the full 128MB
> for
> > flash. So in preparation for my boards arrival, I'm thinking I can do
> this
> > for the flash:
>
> The TLB size is wrong.  It can't be 128M, because Book E only allows
> specifying powers of 4 for the size.  So to do 128M, you need to use
> two TLB entries to specify 128M.
>
> The LAWs *also* need to have full 128M, but they can do any power of two.
>
> Andy
>


Thanks Andy, things are getting clearer. I found another example that seems
to have a bad comment, from the board/tqm85xx/init.S out of u-boot 1.2.0 .
TLB 0, 1 does this which seems to be a good example:

      /*
         * TLB 0, 1:    128M    Non-cacheable, guarded
         * 0xf8000000   128M    FLASH
         * Out of reset this entry is only 4K.
         */
        .long TLB1_MAS0(1, 1, 0)
        .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
        .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
        .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
        .long TLB1_MAS0(1, 0, 0)
        .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
        .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x4000000),
0,0,0,0,1,0,1,0)
        .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x4000000),
0,0,0,0,0,1,0,1,0,1)

But then the LAW comments say this, is this wrong?

 * 0xfe00_0000     0xffff_ffff     FLASH (boot bank)       32M

The actual LAW macros looks right though, doesn't it?

#define LAWBAR2 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff)
#define LAWAR2  (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE &
LAWAR_SIZE_128M))

Robert
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