[U-Boot-Users] Manual setup of DDR2

[robert lazarski]

Hi all, running u-boot 1.2.0 on my custom board with a mpc8548E . I
have 1GB of DDR2, with no other type of SDRAM. I noticed these
comments in the TQM_85xx init.S :

* Without SPD EEPROM configured DDR, this must be setup manually.

So I configured my TLB as follows:

/*
 * DDR Setup
 */
#define CFG_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory*/
#define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE

        /*
         * TLB 7:       1024M   DDR, cache disabled (needed for memory test)
         * 0x00000000  1024M    DDR System memory
         * Without SPD EEPROM configured DDR, this must be setup manually.
         * Make sure the TLB count at the top of this table is correct.
         */
        .long TLB1_MAS0(1, 7, 0)
        .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1GB)
        .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,1,0,1,0)
        .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)

However, I noticed the other 85xx boards - like the CDS ones - have
both 'DDR' and 'SDRAM' , and none of them use a TLB to configure DDR.
My initdram() is below, using the default spd_sdram() :

long int
initdram(int board_type)
{
        long dram_size = 0;
        volatile immap_t *immap = (immap_t *)CFG_IMMR;

        puts("Initializing\n");
        dram_size = spd_sdram();
        puts("    DDR: ");
        return dram_size;
}

Is this the right approach? Just got the bare board today - it'll be a
few weeks until I can run the code. My LAW and memory map is:

*
 * LAW(Local Access Window) configuration:
 *
 * 0x0000_0000     0x7fff_ffff     DDR                     2G
 * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
 * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
 * 0xe000_0000     0xe000_ffff     CCSR                    1M
 * 0xe200_0000     0xe20f_ffff     PCI1 IO                 1M
 * 0xe210_0000     0xe21f_ffff     PCI2 IO                 1M
 * 0xf800_0000     0xffff_ffff     FLASH (boot bank)       128M
 *
 * Notes:
 *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
 *    If flash is 8M at default position (last 8M), no LAW needed.
 *
 * The defines below are 1-off of the actual LAWAR0 usage.
 * So LAWAR3 define uses the LAWAR4 register in the ECM.
 */

#define LAWBAR0 0
#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_1G)) & ~LAWAR_EN)

#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
#define LAWAR1  (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))

#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
#define LAWAR2  (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))

#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
#define LAWAR3  (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))

#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
#define LAWAR4  (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))

#define LAWBAR5 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff)
#define LAWAR5  (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))

Any advice appreciated,
Robert